Word Line Driver Self-Boosting Circuit Mitigates Hot Carrier Degradation
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Solution Overview
Problem
Word line drivers in memory devices experience prolonged read-to-precharge time due to hot carrier degradation of nFETs, leading to an ineffective transition of the word line signal to a logic low level, which affects the reliability and efficiency of memory access operations.
Innovation Solution
The implementation of a word line driver design that includes a transistor configuration with a self-boosting mechanism to lower the drain-source voltage of the nFET, utilizing a negative voltage signal to facilitate quicker transition of the word line to a logic low level, thereby reducing hot carrier degradation and improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional word line driver with pFET and nFET is used to activate and deactivate word lines, then the word line can be switched between logic high and logic low levels, but hot carrier degradation of the nFET causes prolonged read-to-precharge time and ineffective transition to logic low level
Solution Approach 1:
The word line driver is segmented into multiple functional blocks: a conventional complementary FET output stage (pFET and nFET) and a separate self-boosting circuit. The self-boosting circuit is further divided into a self-boosting nFET coupled to the nFET drain and a self-boosting pFET coupled to the pFET source. This segmentation allows the self-boosting circuit to independently regulate transistor gate voltages, compensating for hot carrier degradation effects and maintaining reliable word line switching without extending read-to-precharge time.
Solution Approach 2:
The self-boosting circuit implements a feedback mechanism where the self-boosting nFET's gate voltage is controlled by a self-boosting control signal that responds to the voltage at the nFET drain. Similarly, the self-boosting pFET's gate voltage is controlled by a self-boosting control signal responsive to the pFET source voltage. This feedback allows the circuit to dynamically adjust transistor operating conditions, ensuring effective word line deactivation despite hot carrier degradation of the nFET over time.
2Speed
If the nFET is used to pull the word line down to logic low level, then the word line can be deactivated quickly, but hot carrier degradation prevents effective transition to logic low level within the designed tRP
Solution Approach 1:
The self-boosting nFET acts as an intermediary device between the word line driver output and the nFET. By coupling the self-boosting nFET's drain to the nFET drain and controlling its gate with a self-boosting control signal, it mediates the voltage regulation at the nFET drain node. This intermediary mechanism ensures that the word line can transition to logic low level reliably, compensating for nFET degradation without requiring faster switching speeds that would increase stress on the already degraded transistor.
Solution Approach 2:
The self-boosting circuit dynamically changes the operating parameters (gate voltages) of the pFET and nFET to maintain reliable word line switching. The self-boosting control signals adjust the gate voltages of the self-boosting transistors based on their respective source/drain voltages, effectively changing the electrical parameters of the word line driver to compensate for hot carrier degradation and ensure proper logic level transitions.
Data Source
AI summary
Methods and apparatuses of providing word line voltages are disclosed. An example method includes: activating and deactivating a word line. Activating the word line includes: rendering the first, second and third transistors conductive, non-conductive and non-conductive, respectively, wherein the first transistor is rendered conductive by supplying a gate of the first transistor with a first voltage; and supplying the first node with an active voltage. Deactivating the word line includes: changing a voltage of the first node from the active voltage to an inactive voltage; changing a voltage of the gate of the first transistor from the first voltage to a second voltage, wherein the first transistor is kept conductive by the second voltage; rendering the third transistor conductive during the gate of the first transistor being at the second voltage; and rendering the first and second transistors non-conductive and conductive, respectively, after the third transistor has been rendered conductive.