Word Line Driver Circuit Layout Uniformity

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Solution Overview

Problem

The existing word line driver circuits in semiconductor memory devices experience uneven driving forces and increased leakage current due to varying intervals between drain contacts and gate regions, leading to inconsistent activation of word lines and inefficient transistor performance.

Innovation Solution

The word line driver circuit is designed with drain contacts and gate regions disposed at uniform intervals, ensuring all transistors receive consistent driving forces by arranging them in a specific layout where gate regions overlap and protrude to maintain constant widths, except at connection points, thereby stabilizing the activation of word lines.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If drain contacts and gate regions are arranged with varying intervals, then the layout can be compact, but the driving force becomes uneven and leakage current increases

Engineering Contradiction:
Improvelayout compactnessVSAvoiddriving force uniformity
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent applies local quality by making the interval between drain contacts and gate regions uniform specifically in critical areas where transistors are connected, while allowing flexibility in other layout regions. This localized uniformity ensures consistent driving force for word line activation without requiring complete uniformity throughout the entire layout, thus resolving the contradiction between compactness and reliability.

Inventive Principle:
Principle #3Local quality

2Adaptability or versatility

If drain contacts and gate regions are arranged with varying intervals, then layout flexibility is improved, but leakage current increases

Engineering Contradiction:
Improvelayout flexibilityVSAvoidleakage current
Core Design Contradiction:
Adaptability or versatilityVSObject-generated harmful factors

Solution Approach 1:

The invention applies local quality by enforcing uniform intervals only in specific critical regions where drain contacts connect to gate regions, while maintaining layout flexibility in non-critical areas. This localized approach prevents leakage current generation at transistor connections without restricting overall layout design freedom, thus resolving the contradiction between layout flexibility and leakage current reduction.

Inventive Principle:
Principle #3Local quality

3Reliability

If uniform intervals are maintained between drain contacts and gate regions, then driving force uniformity is improved, but layout design complexity increases

Engineering Contradiction:
Improvedriving force uniformityVSAvoidlayout design complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent reduces layout design complexity by applying uniform interval requirements only to specific critical regions where drain contacts connect to gate regions, rather than enforcing uniformity across the entire layout. This localized approach maintains driving force uniformity where needed while simplifying the overall layout design process, thus resolving the contradiction between reliability and design complexity.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS9318175B1Word line driver circuit for semiconductor memory device
Publication Date: 2016.04.19 SK HYNIX INC
  • US9318175B1 patent drawing
  • US9318175B1 patent drawing
  • US9318175B1 patent drawing

AI summary

A word line driver circuit may include a first active region, a second active region spaced apart from the first active region in a first direction and spaced apart from the first active region in a first direction and spaced apart from the first active region in a second direction, which is substantially perpendicular to the first direction, first contacts formed at both ends of each of the first and second active regions, second contacts formed in the first and second active regions between the first contacts, a gate region between the first contact formed on a second end of the first active region and the second contact and between the first contact formed on a first end of the second active region and the second contact in a straight line, counterclockwise surrounding a part of the second contact formed in the first active region, and clockwise surrounding a part of the second contact formed in the second active region.