Word Line Driving Circuit Defect Detection via Potential Difference
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Solution Overview
Problem
In Dynamic Random Access Memory (DRAM), Poly-Gate necking in Word Line (WL) driving circuits leads to increased resistance and signal distortion, reducing chip yield, and existing methods are inadequate for detecting these defects effectively.
Innovation Solution
A defect detecting method and device for WL driving circuits, which involves selecting multiple WLs, writing specific potentials into memory cells, and reading real-time potentials to identify defects by determining differences greater than a pre-set value, specifically utilizing a first potential and a second potential difference of at least 0.6 V to determine circuit defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If Poly-Gate necking detection is implemented using conventional methods, then detection capability is limited, but device complexity and testing time increase
Solution Approach 1:
The patent segments the WL driving circuit testing into multiple independent test groups, where each group contains multiple WLs that can be tested simultaneously. By dividing the circuit into segments (test groups with different enable signals), the system achieves comprehensive defect detection without requiring complex sequential testing of each WL individually, thus improving measurement precision while controlling device complexity
Solution Approach 2:
The patent implements a universal test architecture where a single test circuit can detect defects across multiple WLs simultaneously by using enable signals to activate different test groups. The same detection mechanism serves multiple functions by selectively enabling different WL groups, eliminating the need for separate detection circuits for each WL and reducing overall system complexity
2Measurement precision
If comprehensive WL driving circuit testing is performed on all WLs, then defect detection accuracy improves, but testing time and productivity decrease
Solution Approach 1:
The patent merges multiple WL tests into simultaneous test operations by organizing WLs into test groups that can be activated concurrently through enable signals. Multiple detection operations are combined into a single testing cycle, allowing comprehensive defect detection across all WLs while maintaining high testing throughput, thus resolving the contradiction between detection accuracy and productivity
Solution Approach 2:
The patent employs periodic activation of different test groups using enable signals that sequentially activate different sets of WLs for testing. This periodic action allows the system to cycle through different test groups efficiently, ensuring comprehensive coverage of all WLs while maintaining continuous testing flow and high productivity
3Reliability
If multiple test groups with different enable signals are used, then defect detection coverage increases, but control circuit complexity increases
Solution Approach 1:
The patent implements preliminary organization of WLs into predetermined test groups with assigned enable signals before testing begins. This preliminary action allows the control circuit to simply activate pre-defined groups without complex real-time decision-making, achieving comprehensive defect detection coverage while keeping control circuit complexity manageable through pre-planned test group configurations
Data Source
AI summary
A defect detecting method for a Word Line (WL) driving circuit includes: m WLs correspondingly connected to m different WL driving circuits are selected from a memory cell array and corresponding WL driving circuit arrays to serve as m WLs to be tested, one of which is set as a first WL and the remaining m-1 ones are set as second WLs; first potential is written into memory cells correspondingly connected to the m WLs to be tested; second potential is written into memory cells correspondingly connected to the first WL; real-time potentials of the memory cells connected to respective second WLs are sequentially read, and when difference value between the real-time potential of one target memory cell and the first potential is greater than first pre-set value, it is determined that the WL driving circuit connected to the second WL corresponding to the target memory cell has a defect.