Flash Memory Word Line Patterning to Prevent Etch Shorts
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Solution Overview
Problem
The challenge in manufacturing flash memory devices is the occurrence of short circuits and sidewall damage due to incomplete or over-etching during the word line structure patterning process, which affects the device yield and reliability.
Innovation Solution
A method involving the formation of a second opening in the second gate layer over a first opening, followed by an anisotropic etching process to pattern a word line structure with protrusions, using a patterned photoresist layer as a mask to avoid incomplete etching and minimize sidewall damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the etching process is intensified to ensure complete removal of the conductor layer, then the completeness of etching is improved, but the sidewalls of the word line structure are damaged due to over-etching
Solution Approach 1:
The method forms a second opening in the second gate layer that is wider than the first opening before the final etching process. This preliminary structural preparation allows the etching process to proceed more smoothly and completely through the conductor layer without requiring excessive etching depth, thereby preventing sidewall damage while ensuring complete etching.
Solution Approach 2:
The etching process is divided into multiple stages with different masking configurations. The first opening and second opening are formed at different levels and widths, allowing the etching to be performed in a controlled manner that ensures completeness without over-etching and damaging the sidewalls.
2Reliability
If the etching process is reduced to preserve sidewalls, then the sidewall integrity is improved, but incomplete etching results in short circuits between word lines
Solution Approach 1:
The second opening is formed in advance with a wider width than the first opening, creating a tapered structure that facilitates complete etching of the conductor layer. This preliminary geometric preparation ensures that the etching process can achieve complete removal of the conductor material without requiring aggressive etching conditions that would damage the sidewalls.
Solution Approach 2:
The method changes the geometric parameters of the openings at different levels. The second opening has a larger width than the first opening, creating a stepped or tapered profile that optimizes the etching process by providing adequate clearance for complete conductor layer removal while maintaining controlled etching depth to protect sidewalls.
3Productivity
If the device dimensions are scaled down to increase component density, then the component density is improved, but the manufacturing complexity and risk of defects increase
Solution Approach 1:
The gate structure is segmented into multiple levels with different opening widths. The first opening and second opening are formed at different depths and have different dimensions, allowing precise control of the etching process at each level. This segmentation enables reliable manufacturing of scaled-down devices by breaking down the complex patterning into manageable steps.
Solution Approach 2:
The method performs preliminary formation of the second opening with optimized dimensions before the final etching step. This preliminary action at the nanoscale enables precise control of the word line structure geometry, ensuring high manufacturing precision and device yield even as device dimensions are scaled down to increase component density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents short circuits and sidewall damage, maintaining memory device yield and manufacturing progress by ensuring complete etching without over-etching, thus enhancing the reliability of the word line structure.
Implementation Method 1
The etching process includes an anisotropic etching process
Implementation Method 2
forming a patterned photoresist layer on the second gate layer. The method further includes using the patterned photoresist layer as a mask, patterning the second gate layer to form a second opening
Data Source
AI summary
A method for forming a semiconductor structure is provided. The method includes providing a substrate with active regions, forming a first gate layer on the active regions of the substrate, and conformally forming an inter-gate dielectric layer on the substrate and the first gate layer. The inter-gate dielectric layer forms a first opening between the first gate layer. The method includes forming a second gate layer on the inter-gate dielectric layer, wherein the second gate layer is filled in the first opening, forming a patterned photoresist layer on the second gate layer, and using the patterned photoresist layer as a mask and patterning the second gate layer to form a second opening. The second opening is directly over the first opening. The method further includes patterning the second gate layer, the inter-gate dielectric layer, and the first gate layer to form a word line structure on the substrate.