Word Line Fault Detection in Dual Memory Arrays
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Solution Overview
Problem
Current fault detection techniques in memory circuits are inadequate for detecting no word line, multiple word line, and incorrect word line selection faults in a high percentage of situations, limiting their effectiveness in ensuring successful read and write operations.
Innovation Solution
A circuit with two memory arrays and word line fault detection circuits that encode signals on common word lines to generate encoded values, which are then compared to expected values to detect faults, using comparison circuitry to assert error flags for faulty conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If current fault detection techniques are used in memory circuits, then the circuit complexity is kept low, but the fault detection capability is insufficient for detecting no word line, multiple word line, and incorrect word line selection faults
Solution Approach 1:
The fault detection circuit is segmented into two separate memory arrays, each with its own fault detection circuit. This segmentation allows the system to detect faults in one array without affecting the other, improving overall fault detection capability while maintaining manageable circuit complexity through modular design
Solution Approach 2:
The patent introduces a new dimension to fault detection by using two memory arrays arranged in a specific configuration with shared word lines. This dimensional change enables the detection of fault types (no word line selected, multiple word lines selected, incorrect word line selected) that cannot be detected by traditional single-array methods
2Measurement precision
If two memory arrays with fault detection circuits are implemented, then the fault detection accuracy is improved, but the area of the circuit increases
Solution Approach 1:
The patent merges two memory arrays by sharing common word lines between them. This merging approach allows the fault detection circuits to utilize the same physical word line infrastructure, improving fault detection accuracy through cross-array comparison while reducing the overall circuit area that would be required for completely separate arrays
Solution Approach 2:
The common word lines serve multiple functions: they are used for normal memory operations in both arrays and simultaneously serve as the basis for fault detection. This multi-functionality allows the same physical structures to perform dual purposes, improving detection accuracy without proportionally increasing circuit area
Data Source
AI summary
First and second memory arrays have common word lines driven by a row decoder in response to a row address. A first word line encoder associated with the first memory array encodes signals on the word lines to generate a first encoded value, and a second word line encoder associated with the second memory array encodes signals on the word lines to generate a second encoded value. Comparison circuitry compares the first encoded value to a first expected value (e.g., a first portion of the row address) and compares the second encoded value to a second expected value (e.g., a second portion of the row address). An error flag is asserted to indicate presence of a word line fault based upon a lack of match between the first encoded value and the first expected value and/or a lack of match between the second encoded value and the second expected value.