Word Line Floating Control to Prevent Adjacent Memory Cell Data Loss
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Solution Overview
Problem
As the degree of integration in semiconductor devices increases, the distance between word lines decreases, leading to data loss in memory cells connected to unselected word lines due to parasitic capacitance effects during voltage transitions.
Innovation Solution
A semiconductor device is designed with a word line driving circuit and control logic that causes at least one unselected word line adjacent to the selected word line to float during a portion of the period when the selected word line's voltage returns to its initial level, thereby minimizing data loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the degree of integration is increased to improve device density, then the distance between word lines decreases, but data loss in unselected memory cells increases due to parasitic capacitance effects
Solution Approach 1:
The patent applies preliminary action by pre-charging unselected word lines to a voltage level higher than the initial level before the selected word line voltage transitions. This preliminary voltage adjustment creates a voltage buffer that counteracts the parasitic capacitance coupling effects, preventing data loss in unselected memory cells while maintaining high device density
Solution Approach 2:
The patent changes the voltage parameter of unselected word lines dynamically. During the selected word line activation period, unselected word lines are maintained at a voltage level higher than the initial level (pre-charged state). This parameter change compensates for the reduced distance between word lines, allowing high integration density without causing data loss through parasitic capacitance coupling
2Length of stationary object
If the distance between word lines is decreased to improve integration, then more memory cells fit in the same area, but parasitic capacitance effects cause data loss in unselected memory cells
Solution Approach 1:
The patent changes the voltage parameter of unselected word lines from the initial level to a higher pre-charged level during selected word line activation. This parameter change creates an electrical buffer that counteracts the strong parasitic capacitance coupling caused by the reduced distance between word lines, preventing data loss while maintaining compact integration
Solution Approach 2:
The patent applies preliminary anti-action by pre-charging unselected word lines to a higher voltage level before the selected word line transitions. This preliminary voltage adjustment creates a counteracting electrical field that offsets the harmful parasitic capacitance effects, preventing data loss in unselected memory cells despite the reduced word line spacing
3Device complexity
If unselected word lines are maintained at initial level during selected word line transition, then circuit operation is simple, but data loss occurs in unselected memory cells connected to adjacent word lines
Solution Approach 1:
The patent changes the voltage parameter of unselected word lines dynamically during operation. Control logic adjusts the voltage of unselected word lines to a level higher than the initial level during the selected word line activation period, then returns them to the initial level afterward. This parameter change prevents data loss while managing circuit complexity through controlled voltage adjustment
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces data loss in unselected memory cells by allowing the voltage of unselected word lines to decrease to a level lower than the initial level, thus reducing stress and preventing data changes during voltage transitions.
Implementation Method 1
data loss in memory cells connected to unselected word lines due to parasitic capacitance effects during voltage transitions
Data Source
AI summary
A semiconductor device includes a memory cell array that includes a plurality of memory cells electrically connected to a plurality of word lines and a plurality of bit lines, a word line driving circuit that includes a plurality of sub-word line decoders electrically connected to the plurality of word lines, and a control logic configured to determine a selected word line and unselected word lines among the plurality of word lines, and configured to control the word line driving circuit such that at least one of the unselected word lines that is adjacent to the selected word line is floated during at least a portion of a period in which a voltage of the selected word line returns to an initial level.