3D Memory Word Line Floating Time Control

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In three-dimensional memory devices, the erase operation in sub-block units can cause a disturb phenomenon where adjacent sub-blocks are inadvertently erased, leading to unexpected changes in the threshold voltage distribution of memory cells, necessitating a method to control the floating time point of word lines connected to adjacent sub-blocks during erase operations.

Innovation Solution

The memory device includes a voltage generator and control logic that divide word lines connected to adjacent sub-blocks into groups, allowing for the differential setting of floating time points for each group, gradually decreasing voltage from the center to the edge of the sub-block to prevent disturb phenomena during erase operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If erase operation is performed on a sub block, then data in the sub block is erased, but adjacent sub blocks experience disturb phenomenon and threshold voltage distribution changes

Engineering Contradiction:
Improveerase operation reliabilityVSAvoiddisturb phenomenon in adjacent sub blocks
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent divides word lines into multiple groups (first group, second group, third group) and applies different floating time points to each group during the erase operation. This segmentation allows selective control of voltage application timing to different regions of the memory device, preventing disturb phenomena in adjacent sub blocks while maintaining effective erase operation in the target sub block.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements different floating time points for different groups of word lines based on their spatial location. The first group (connected to center portion) receives a different floating time point than the second group (connected to one end) and third group (connected to the other end). This local differentiation optimizes the erase operation by addressing the specific needs of each region, preventing disturb phenomena in adjacent sub blocks while ensuring thorough erasure in the target sub block.

Inventive Principle:
Principle #3Local quality

2Productivity

If word lines are floated simultaneously, then erase operation is efficient, but adjacent sub blocks are inadvertently affected

Engineering Contradiction:
Improveerase operation speedVSAvoidintegrity of adjacent sub blocks
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary floating action to specific groups of word lines at different time points before completing the erase operation. By floating the first group of word lines (connected to center portion) at a different time point than the second and third groups (connected to ends), the patent prepares the voltage distribution in advance to prevent disturb phenomena in adjacent sub blocks while maintaining efficient erase operation in the target sub block.

Inventive Principle:
Principle #10Preliminary action

3Device complexity

If uniform voltage is applied to all word lines, then control is simplified, but threshold voltage distribution in adjacent sub blocks changes unexpectedly

Engineering Contradiction:
Improvecontrol logic complexityVSAvoidthreshold voltage distribution control
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The patent introduces dynamic control by varying the floating time points for different groups of word lines during the erase operation. Instead of a static uniform voltage application, the system dynamically adjusts when each group of word lines is floated based on their spatial location and connection to different portions of the sub block. This dynamic approach enables precise control of threshold voltage distribution in adjacent sub blocks while maintaining manageable control logic through systematic grouping.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11335410B2Memory device and method of operating the same
Publication Date: 2022.05.17 SK HYNIX INC
  • US11335410B2 patent drawing
  • US11335410B2 patent drawing
  • US11335410B2 patent drawing

AI summary

A memory device that controls a floating time point of word lines connected to a sub block adjacent to a sub block on which an erase operation is performed includes a plurality of memory blocks each including a plurality of sub blocks, a voltage generator configured to generate a plurality of voltages to perform an erase operation on any of the plurality of sub blocks, and control logic configured to divide a plurality of word lines connected to an adjacent sub block neighboring a sub block on which the erase operation is performed into a plurality of groups, and configured to control the voltage generator to differently set a floating time point of word lines included in each group for each of the plurality of groups, during the erase operation.