Word Line Group Decoder for Parallel Memory Control
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Solution Overview
Problem
Current semiconductor storage devices face limitations in controlling memory cell arrays due to restricted flexibility when all word line groups are activated in parallel, as only a corresponding word line can be selectively driven, hindering appropriate control based on device commands.
Innovation Solution
Incorporating a row decoder with multiple word line group decoders that can independently drive different word lines within each word line group when all groups are activated in parallel, allowing for selective control of memory cells across the array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single word line group decoder is used to control multiple word line groups, then the device complexity is reduced, but the flexibility in controlling memory cells is insufficient
Solution Approach 1:
The row decoder is segmented into multiple independent word line group decoders (first word line group decoder, second word line group decoder, etc.), each responsible for controlling a specific word line group. This segmentation allows each decoder to independently select and drive its corresponding word line group, thereby increasing control flexibility without requiring a single complex decoder to manage all word line groups.
Solution Approach 2:
The patent introduces a new dimension of control by adding multiple decoders operating in parallel across different word line groups. Instead of a single decoder handling all groups sequentially or collectively, the system expands the decoder architecture into multiple independent units, each operating on its own dimension (word line group), thereby achieving both reduced complexity per decoder and increased overall flexibility.
2Speed
If all word line groups are activated in parallel with a single decoder, then the operational speed is improved, but the ability to selectively drive specific word lines is restricted
Solution Approach 1:
By dividing the row decoder into multiple specialized decoders (first word line group decoder for even word lines, second word line group decoder for odd word lines), each decoder can independently and simultaneously activate its assigned word lines. This segmentation enables parallel operation across all word line groups while maintaining the ability to selectively drive specific word lines within each group, resolving the contradiction between speed and selective control.
Solution Approach 2:
The patent implements dynamic control where each word line group decoder can independently activate or deactivate its corresponding word line group based on operational requirements. This dynamic capability allows the system to flexibly adjust which word lines are driven during parallel operations, enabling both high-speed parallel activation and selective control of specific word lines as needed.
Data Source
AI summary
A semiconductor storage device includes a memory cell array including a plurality of word line groups and a plurality of blocks corresponding to the plurality of word line groups. Each of word line groups includes a plurality of word lines and each of the blocks includes a plurality of memory cells. The plurality of memory cells of each block are connected to the respective word lines of a corresponding one of the word line groups. The semiconductor storage device includes a row decoder including a plurality of word line group decoders corresponding to the plurality of word line groups, respectively. Each of the plurality of word line group decoders is configured to drive a word line independent from a word line driven in another of the word line groups, when all of the plurality of word line groups are activated in parallel.