Word-Line Leakage Detection via Low Voltage Biasing
Solution Overview
Problem
Defects such as word-line leakage and broken word-lines in flash EEPROM memory devices can lead to data corruption and operational failures, particularly as device sizes scale down, making it challenging to detect these issues effectively after manufacturing and during the device's operational life.
Innovation Solution
A circuit and method that include a comparator, signal generating circuit, and counter circuit to detect current leakage by comparing counts of a gate clock signal or regulation clock signal over an interval with a reference count, allowing for on-chip detection of word-line leakage and broken word-lines, enabling automatic and field-based testing without the need for external test equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device size is scaled down to increase storage density, then storage capacity is improved, but detection of word-line leakage and broken word-lines becomes more difficult
Solution Approach 1:
The patent performs leakage detection before programming operations by monitoring the discharge rate of a capacitor connected to the word line. This preliminary detection identifies defective word-lines with leakage currents exceeding a threshold, preventing subsequent programming operations on faulty lines and ensuring reliable data storage in scaled-down devices.
Solution Approach 2:
The patent replaces complex external test equipment with an integrated on-chip detection circuit that uses a capacitor, voltage source, and counter to monitor word-line leakage. This substitution enables automated detection within the memory device itself, making the system more suitable for scaled-down applications where external testing becomes impractical.
2Measurement precision
If external test equipment is used to detect word-line leakage, then detection accuracy is improved, but device complexity and testing cost increase
Solution Approach 1:
The patent implements a self-service detection system where the memory device monitors its own word-line leakage using an integrated capacitor and voltage source. The circuit charges a capacitor to a reference voltage and measures the discharge rate through the word line, automatically identifying defective lines without requiring external test equipment, thereby reducing system complexity while maintaining detection accuracy.
Solution Approach 2:
The patent uses a multi-functional integrated circuit that serves both as part of the normal memory operation and as a leakage detection system. The same voltage sources and control logic are used for both programming operations and leakage detection, eliminating the need for separate external test equipment and reducing overall system complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables reliable detection of word-line leakage and broken word-lines, preventing data corruption and operational failures by allowing for early identification and correction of defects within the memory system, improving the reliability and longevity of flash EEPROM devices.
Implementation Method 1
a voltage regulating circuit providing a regulated second voltage level according to a first regulation clock signal
Implementation Method 2
determining an indication of current leakage from the second node when the second voltage level is connected to the second node and the first voltage level is connected to the first node
Data Source
AI summary
Techniques are presented for determining current leakage from a memory array or other circuit based on a low voltage path. For example, the technique can be applied to determine word line to word line leakage. By looking at a count for the clock used in regulating the low voltage output node, the amount of leakage can be determined. The leakage determination can be performed as part of test process or during normal memory operations.