Word Line Leakage Detection Using Grouped Pass Transistors
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Solution Overview
Problem
Non-volatile memory devices suffer from word line leakage due to deterioration, leading to malfunctions, and existing methods are inadequate for efficient detection of such leakage.
Innovation Solution
A memory device with a pass transistor circuit and a control circuit that applies specific voltage levels to word lines and select lines to rapidly detect leakage by setting detection word lines to different voltage levels, enabling quicker identification of leakage across multiple word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional leakage detection methods are used, then leakage can be detected, but the detection process is slow and inefficient
Solution Approach 1:
The memory block is divided into multiple word line groups, with each group assigned to a separate pass transistor. The control circuit independently controls the voltage level of each word line group, enabling parallel leakage detection across multiple word lines simultaneously, thereby reducing total detection time while maintaining accuracy
Solution Approach 2:
The control circuit pre-configures the voltage levels of multiple word lines before the actual leakage detection begins. By setting up the voltage distribution in advance and preparing the pass transistor circuitry, the system eliminates setup delays during the detection process itself, achieving faster overall detection without compromising measurement precision
2Productivity
If multiple word lines are detected simultaneously, then detection speed improves, but device complexity increases
Solution Approach 1:
The pass transistor circuit is designed with universal functionality where each pass transistor can independently control any word line group. The same circuit architecture and control logic are reused across all word line groups, enabling parallel operation without proportionally increasing hardware complexity. This multi-functional design allows the system to detect multiple word lines simultaneously using a standardized, scalable circuit approach
Data Source
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AI summary
In some embodiments, the memory device includes a memory cell array including a plurality of memory blocks including a plurality of word lines, a pass transistor circuit including a plurality of pass transistors coupled to the plurality of word lines, a row decoder configured to provide a block selection voltage to first terminals and a driving voltage to second terminals of the plurality of pass transistors, a voltage generator configured to generate the block selection voltage and the driving voltage, and a control circuit configured to control the row decoder and the voltage generator, perform a leakage detection operation on a target memory block of the plurality of memory blocks, set a plurality of first detection word lines of the target memory block to a first voltage level, and set a plurality of second detection word lines of the target memory block to a second voltage level.