Semiconductor Memory Word Line Leakage Detection
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in detecting leakage between word lines, particularly in user mode, as existing methods require a test mode for detection and cannot detect leakage that occurs post-shipment.
Innovation Solution
A semiconductor memory device with a voltage boosting circuit that applies different voltages to word lines and uses a counter and determination circuit to measure clock cycles, comparing the number of reference clocks and evaluation clocks to detect leakage, allowing for real-time detection in user mode during verification and read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a test mode is used to detect leakage between word lines, then leakage detection capability is provided, but operational speed is reduced and detection cannot occur in user mode
Solution Approach 1:
The patent makes the leakage detection function dynamic by enabling it to operate in both test mode and user mode. The determination circuit dynamically switches between different detection scenarios: in test mode, it detects leakage during program operations, while in user mode, it continuously monitors for leakage during verification and read operations. This dynamic operation eliminates the need to switch between test and user modes for different detection scenarios, thereby maintaining operational speed while providing continuous leakage detection capability.
Solution Approach 2:
The patent implements a universal leakage detection mechanism that functions across multiple operational modes (test mode and user mode) and multiple operational types (program, verification, and read operations). The voltage boosting circuit and determination circuit work together to provide a unified leakage detection approach that adapts to different operational contexts, eliminating the limitation where leakage detection could only occur in test mode and enabling continuous monitoring throughout the device's operational lifecycle.
2Reliability
If leakage detection is performed during program operations, then weak leakage can be identified early, but the time required for program operations increases
Solution Approach 1:
The patent applies partial action by performing leakage detection selectively during specific program operations rather than continuously. The determination circuit monitors program operations and identifies weak leakage conditions, but only triggers extended detection or corrective actions when leakage is actually detected. This partial application of leakage detection during program operations allows early identification of weak leakage while minimizing the additional time required, as the detection is performed only when necessary rather than as a continuous overhead.
3Reliability
If continuous leakage monitoring is implemented in user mode, then data corruption is prevented, but device complexity increases
Solution Approach 1:
The patent merges the leakage detection function with existing operational circuits by utilizing the voltage boosting circuit that is already present for normal word line operations. The determination circuit is integrated into the existing control logic, and leakage detection during verification and read operations leverages the same infrastructure used for these operations. This merging approach enables continuous leakage monitoring in user mode without significantly increasing device complexity, as the detection functionality is combined with existing operational components rather than requiring separate dedicated monitoring hardware.
Data Source
AI summary
A semiconductor memory device includes a first word line and a second word line that are adjacent to each other, a first voltage boosting circuit configured to generate a first voltage based on a clock signal, a second voltage boosting circuit configured to generate a second voltage lower than the first voltage based on the clock signal, a counter, and a determination circuit. The counter counts a first number of clock cycles of the clock signal during a first period in which the first voltage boosting circuit generates the first voltage and applies the first voltage to the first word line while the second voltage boosting circuit generates the second voltage and applies the second voltage to the second word line, and a second number of clock cycles of the clock signal during a second period in which the first voltage boosting circuit generates the first voltage while the first word line is electrically disconnected from the first voltage boosting circuit. The determination circuit compares the first number of clock cycles and the second number of clock cycles to determine whether or not a leakage exists in the word lines.