Cross-Point Memory Word Line Layout for Offset Via Connections
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Solution Overview
Problem
The connection between word lines and lower conductive vias in cross-point memory arrays is prone to issues such as charge carrier buildup leading to transistor breakdown and galvanic corrosion, which affects the performance and yield of the memory array.
Innovation Solution
The conductive vias and wires in the interconnect structure are offset from the bottom surface of the word lines, and upper conductive vias are formed after the word lines to disperse charge carriers and prevent galvanic corrosion, ensuring stable electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If word lines are connected to lower conductive vias in cross-point memory arrays, then electrical connection is established, but charge carrier buildup occurs leading to transistor breakdown and galvanic corrosion
Solution Approach 1:
The patent extracts the problematic lower conductive vias and wires from direct contact with word lines by offsetting them horizontally. This separation removes the source of charge carrier buildup and galvanic corrosion while maintaining electrical connectivity through alternative upper conductive paths that do not suffer from these harmful effects
Solution Approach 2:
The patent introduces upper conductive vias and wires as intermediary elements to establish electrical connection between word lines and the rest of the circuit. These upper intermediaries are positioned to avoid charge carrier buildup and galvanic corrosion issues that affect lower conductive paths, thereby mediating the connection in a harmful-factor-free manner
2Ease of manufacture
If conventional interconnect structure is used with word lines directly contacting lower conductive vias, then manufacturing is simplified, but transistor breakdown and delamination occur
Solution Approach 1:
The patent segments the interconnect structure into distinct lower and upper conductive systems. Lower conductive vias and wires are offset from word lines, while upper conductive vias and wires provide the actual connection path. This segmentation allows each component to be optimized independently, improving reliability without significantly complicating the manufacturing process
Solution Approach 2:
The patent moves the conductive connection path from the lower dimension (below word lines) to the upper dimension (above word lines). By forming upper conductive vias and wires that contact the top surface of word lines, the connection is established in a different spatial dimension, avoiding the harmful effects present in the lower dimension while maintaining manufacturing feasibility
Data Source
AI summary
Various embodiments of the present application are directed towards an integrated chip including a first conductive interconnect structure overlying a substrate. A first memory stack is disposed on the first conductive interconnect structure. A second conductive interconnect structure overlies the first memory stack. The second conductive interconnect structure is spaced laterally between opposing sidewalls of the first conductive interconnect structure. A third conductive interconnect structure is disposed on the first conductive interconnect structure. A top surface of the third conductive interconnect structure is vertically above the second conductive interconnect structure.