Word Line Width Control to Prevent DRAM Overlay Shorts

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Solution Overview

Problem

DRAM manufacturers face challenges in minimizing memory cell area due to reduced word line spacing, leading to electrical shorts caused by overlay errors in the lithography process.

Innovation Solution

A method of manufacturing semiconductor devices that uses a width controlling structure to determine the width of word lines without relying on photolithography, allowing for accurate control of word line width and preventing electrical leakage by forming word lines between sacrificial layers and patterning the metallization layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If photolithography is used to pattern word lines, then manufacturing process is simple, but overlay errors cause electrical shorts between channel and word line

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoidelectrical isolation between channel and word line
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

A mandrel structure is introduced as an intermediary element to define the word line pattern. The mandrel is formed before the word line metallization and serves as a physical template that ensures proper spacing and alignment, eliminating overlay errors while maintaining process simplicity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The mandrel structure is formed in advance before the word line patterning step. This preliminary structure guides subsequent processing steps and ensures accurate word line placement without relying on photolithographic alignment, preventing electrical shorts between channel and word line.

Inventive Principle:
Principle #10Preliminary action

2Area of stationary object

If word line spacing is reduced to minimize memory cell area, then device density increases, but electrical shorts occur due to overlay errors

Engineering Contradiction:
Improvememory cell areaVSAvoidelectrical isolation
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The mandrel acts as a mediator that physically separates and spaces the word lines at reduced pitch. By using the mandrel's physical dimensions rather than photolithographic alignment, accurate spacing is achieved even at minimal memory cell areas, preventing electrical shorts.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Ease of manufacture

If photolithography alignment is used to control word line width, then process is straightforward, but overlay errors reduce manufacturing precision

Engineering Contradiction:
Improvepatterning process simplicityVSAvoidword line width control
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The mandrel structure serves as a precision template that physically defines the word line width and position. This intermediary approach replaces photolithographic alignment with direct physical contact and conformal deposition, achieving superior manufacturing precision while keeping the process straightforward.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent replaces the optical alignment system (photolithography) with a mechanical/physical system (mandrel-based conformal deposition). The mandrel's physical presence and dimensions directly control word line geometry, eliminating overlay errors and improving width control precision.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS12178037B2Method of manufacturing semiconductor device with word lines
Publication Date: 2024.12.24 NAN YA TECH
  • US12178037B2 patent drawing
  • US12178037B2 patent drawing
  • US12178037B2 patent drawing

AI summary

The present disclosure provides a method of manufacturing a semiconductor device. The method includes providing a substrate, forming a metallization layer on the substrate, forming an upper dielectric layer over the metallization layer, forming a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer penetrating the upper dielectric layer and the metallization layer, wherein the first sacrificial layer is aligned with the third sacrificial layer along a first axis, and the second sacrificial layer is free from overlapping the first sacrificial layer and the third sacrificial layer along the first axis, forming a width controlling structure between the first sacrificial layer and the third sacrificial layer, wherein the width controlling structure defines a recess exposing the upper dielectric layer, forming a protective layer within the recess, removing the width controlling structure to expose a portion of the metallization layer.