Word Line Bonding Pad Layout for Higher-Density 3D Memory
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in optimizing chip area and manufacturing cost due to the distribution of bonding pads and transistors across different chip regions, leading to inefficiencies in cell occupancy and peripheral circuit area utilization.
Innovation Solution
The semiconductor memory device design incorporates a memory chip with transistors and bonding pads strategically placed to reduce the number of bonding pads and increase cell occupancy, allowing for a more efficient layout where the memory cell array is stacked above peripheral circuits, and transistors are distributed to minimize chip area and manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If bonding pads and transistors are distributed across different chip regions in conventional semiconductor memory devices, then manufacturing processes are simplified, but chip area increases and cell occupancy decreases
Solution Approach 1:
The patent merges the functions of bonding pads and transistors by placing transistors directly between bonding pads and word lines in the same chip region. This integration eliminates the need for separate peripheral circuit regions, reducing overall chip area while maintaining manufacturing feasibility through unified process steps.
Solution Approach 2:
The patent utilizes vertical stacking to place memory cell arrays above peripheral circuits including transistors and bonding pads. This three-dimensional arrangement increases cell occupancy by utilizing the vertical dimension, effectively reducing the horizontal chip area required while keeping transistor design complexity manageable through standardized vertical transistor structures.
2Area of moving object
If memory cell array is stacked above peripheral circuits, then cell occupancy increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the chip into distinct functional regions: a first region containing memory cell arrays with stacked word lines, and a second region containing peripheral circuits with transistors and bonding pads. This segmentation allows each region to be optimized independently, improving cell occupancy in the first region while maintaining manageable manufacturing precision requirements in the second region.
Solution Approach 2:
The patent applies different structural characteristics to different regions: the first region uses vertically stacked memory cells optimized for high density, while the second region uses laterally arranged transistors and bonding pads optimized for electrical connectivity. This local optimization achieves high cell occupancy without imposing excessive precision requirements across the entire chip.
3Quantity of substance
If transistors are placed between bonding pads and word lines, then the number of bonding pads is reduced, but transistor design complexity increases
Solution Approach 1:
The patent designs transistors with multi-functional capability to serve both as connection elements between bonding pads and word lines, and as selectable switches for memory cell access. This universal transistor design reduces the number of separate bonding pads needed while avoiding excessive complexity through standardized device structures that perform multiple functions.
Data Source
AI summary
A semiconductor memory device includes a memory chip. The memory chip includes a first region including a plurality of first memory cells and second memory cells, a second region different from the first region, a plurality of first word lines stacked apart from each other in a first direction in the first and second regions, a first pillar including a first semiconductor layer extending through the first word lines, and a first insulator layer provided between the first semiconductor layer and the first word lines, in the first region, the first memory cells being located at intersections of the first pillar with the first word lines, a first bonding pad in the second region, and a first transistor between the first word lines and the first bonding pad, and connected between one of the first word lines and the first bonding pad, in the second region.