Memory Word Line Pass Voltage Compensation Across NAND Layers

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Solution Overview

Problem

Existing non-volatile memory programming techniques face challenges in maintaining reliable threshold voltage margins across different layers of memory cells, leading to inconsistent programming reliability.

Innovation Solution

Adjusting pass voltages applied to unselected word lines using layer-specific biases and temperature-dependent adjustments to improve threshold voltage margins, thereby enhancing programming reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single baseline pass voltage is applied to all unselected word lines, then the device complexity is reduced and ease of operation is improved, but the threshold voltage margin becomes inconsistent across different layers leading to reduced programming reliability

Engineering Contradiction:
Improveprogramming reliabilityVSAvoidpass voltage control complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies different pass voltage offsets to different layers of unselected word lines based on their specific position and interference characteristics. Each layer receives a customized pass voltage (baseline pass voltage plus layer-specific offset) tailored to its local conditions, ensuring optimal threshold voltage margin for each layer while maintaining overall system reliability.

Inventive Principle:
Principle #3Local quality

2Reliability

If layer-specific pass voltage offsets are applied to compensate for inter-layer interference, then the threshold voltage margin and programming reliability are improved, but the device complexity and control difficulty increase

Engineering Contradiction:
Improvethreshold voltage margin consistencyVSAvoidpass voltage application complexity
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The patent segments the unselected word lines into multiple layers, each receiving a specific pass voltage offset. This segmentation allows independent optimization of pass voltages for each layer based on their interference patterns, enabling precise control over threshold voltage margins without requiring complex global adjustments.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent modifies the pass voltage parameter by adding layer-specific offsets to the baseline pass voltage. This parameter change approach allows systematic adjustment of pass voltages across different layers to compensate for inter-layer interference, improving threshold voltage margin consistency while maintaining a structured and manageable control scheme.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If higher pass voltages are applied to unselected word lines to prevent programming, then programming reliability is improved, but the risk of program disturb to adjacent layers increases

Engineering Contradiction:
Improveprogramming accuracyVSAvoidprogram disturb to unselected layers
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies pass voltages with local quality by tailoring the voltage level to each specific layer's needs. Instead of using a uniformly high pass voltage that could cause program disturb, each layer receives a customized pass voltage (baseline plus offset) that is sufficient to prevent programming in that specific layer while minimizing interference with adjacent layers.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12469562B2VPASS auto layer compensation in a memory device
Publication Date: 2025.11.11 SANDISK TECHNOLOGIES LLC
  • US12469562B2 patent drawing
  • US12469562B2 patent drawing
  • US12469562B2 patent drawing

AI summary

The memory device includes a memory block with a plurality of memory cells that are arranged in a plurality of word lines. The word lines are grouped in a plurality of layers. The memory device also includes circuitry that is configured to program the memory cells of a selected word line of the plurality of word lines. The circuitry is configured during programming to determine which layer of the plurality of layers the selected word line is located in. The circuitry is also configured to apply a programming voltage to the selected word line and apply pass voltages to a plurality of unselected word lines. For at least some of the unselected word lines, the pass voltage is a baseline pass voltage level that is adjusted by a layer-unique bias pass voltage.