Word Line Contact Polysilicon Patterning to Prevent Bridging
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in non-volatile memory devices, such as flash memory, is the difficulty in selectively removing polysilicon material between tightly packed polysilicon lines in the strap regions, which can lead to residue and electrical shorts due to decreasing spacing between lines with each technology generation.
Innovation Solution
A patterning process involving photolithography and etching operations is employed to remove excess material between polysilicon lines in the strap regions, using a hard mask stack and selective etching processes to minimize residue and prevent bridging, allowing for tighter spacing without electrical shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If polysilicon lines are packed tighter to increase memory density, then storage capacity increases, but residue and electrical shorts occur due to insufficient spacing
Solution Approach 1:
The patent applies preliminary action by performing multiple preparatory steps before the final polysilicon removal: forming a mandrel structure, depositing spacer materials, and creating a multi-layer mask system. These preliminary structures enable subsequent selective etching processes to successfully remove polysilicon between tightly spaced lines without causing shorts or residue
Solution Approach 2:
The patent uses intermediary structures including mandrels, spacers, and multi-layer masks that mediate between the tightly spaced polysilicon lines. These intermediary elements provide physical separation and control during the etching process, allowing complete polysilicon removal while preventing direct contact between adjacent lines that would cause electrical shorts
2Manufacturing precision
If conventional etching processes are used on tightly packed polysilicon lines, then material removal is achieved, but residue remains and bridging occurs
Solution Approach 1:
The patent segments the etching process into multiple distinct steps with different etchants and parameters. The first etching step uses one set of conditions to remove initial polysilicon, while subsequent steps use different conditions to address remaining residue. This segmentation allows optimization of each step for its specific purpose, achieving complete removal without bridging
Solution Approach 2:
The patent applies parameter changes by varying etching conditions between steps - changing etchant composition, temperature, pressure, and exposure time. These parameter adjustments enable the process to adapt to different removal stages, effectively eliminating residue while maintaining line separation to prevent bridging
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The process effectively reduces or eliminates residue and ensures adequate spacing between contacts, preventing electrical shorts and enhancing the density and storage capacity of memory devices.
Implementation Method 1
A patterning process involving photolithography and etching operations is employed to remove excess material between polysilicon lines
Implementation Method 2
etching, from the mask layer, the polysilicon lines with a dry etching process
Implementation Method 3
etching unremoved portions of the mask layer with a wet etching process
Data Source
AI summary
The present disclosure describes a patterning process for a strap region in a memory cell for the removal of material between polysilicon lines. The patterning process includes depositing a first hard mask layer in a divot formed on a top portion of a polysilicon layer interposed between a first polysilicon gate structure and a second polysilicon gate; depositing a second hard mask layer on the first hard mask layer. The patterning process also includes performing a first etch to remove the second hard mask layer and a portion of the second hard mask layer from the divot; performing a second etch to remove the second hard mask layer from the divot; and performing a third etch to remove the polysilicon layer not covered by the first and second hard mask layers to form a separation between the first polysilicon gate structure and the second polysilicon structure.