Word Line Dependent Programming Voltage for NAND Flash
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Solution Overview
Problem
In NAND flash memory systems, program disturb occurs due to leakage currents such as punch-through conduction, drain-induced barrier lowering (DIBL), and gate-induced drain leakage (GIDL), which can lead to unintended changes in threshold voltage and data loss, especially as memory arrays scale down.
Innovation Solution
The solution involves applying programming conditions that depend on the location of the word line, including varying the width or duration of programming pulses, voltages applied to bit lines, common source lines, and select transistors, to mitigate leakage and maintain the boosted channel voltage, thereby reducing program disturb.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory arrays are scaled down to increase density, then storage capacity is improved, but leakage currents (punch-through conduction, DIBL, GIDL) increase causing program disturb
Solution Approach 1:
The patent applies different voltage conditions to different word lines based on their location. Edge word lines (first and last in the string) receive different programming conditions compared to middle word lines. This local differentiation addresses the varying leakage characteristics at different positions in the scaled-down memory array, preventing program disturb while maintaining high density.
Solution Approach 2:
The patent changes programming parameters (voltage magnitude, pulse width) based on word line location. Edge word lines are programmed with reduced voltage or shorter pulse widths compared to middle word lines. This parameter adjustment compensates for increased leakage currents in scaled-down devices, preventing unintended threshold voltage changes while preserving storage capacity.
2Speed
If programming voltage is applied to all word lines simultaneously, then programming speed is improved, but program disturb occurs due to leakage in inhibited NAND strings
Solution Approach 1:
The patent differentiates programming conditions between edge word lines and middle word lines. Edge word lines are subjected to reduced programming voltage or shorter pulse durations to prevent excessive leakage and program disturb, while middle word lines receive full programming strength. This selective approach maintains overall programming speed while preventing disturbances in vulnerable edge regions.
Solution Approach 2:
The patent applies partial programming action to edge word lines by using reduced voltage or shorter pulses compared to middle word lines. This partial action is sufficient for edge word lines due to their different electrical characteristics, while avoiding the excessive action that would cause program disturb through leakage currents.
3Quantity of substance
If select transistor channel length is reduced to increase density, then storage capacity is improved, but punch-through conduction and DIBL effects increase
Solution Approach 1:
The patent applies preliminary anti-action by using reduced programming voltage or shorter pulse widths on edge word lines before leakage can cause significant program disturb. This preemptive adjustment compensates for the increased punch-through conduction and DIBL effects resulting from reduced select transistor channel lengths, maintaining high density while preventing harmful leakage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces program disturb by optimizing voltage and pulse conditions based on word line location, enhancing data retention and programming accuracy in NAND flash memory systems.
Implementation Method 1
Punch-through conduction may occur due to the difference in the drain to source voltage across the channel of a select gate transistor
Implementation Method 2
Another type of leakage from the channel of inhibited NAND strings may arise due to drain induced barrier lowering (DIBL). DIBL may cause the VTH of the select transistors to drop
Implementation Method 3
Gate induced drain leakage (GIDL) is another problem that may cause program disturb. GIDL refers to charge carriers leaking into the channel from a select transistor as a result of a voltage applied to the gate of one of the select transistors
Data Source
AI summary
Methods and devices for operating non-volatile storage are disclosed. One or more programming conditions depend on the word line that is selected for programming. Applying a selected word line dependent program condition may reduce or eliminate program disturb. The duration of a programming pulse may depend on the word line that is selected for programming. This could be a physical characteristic of the word line or its location on a NAND string. As one example, a shorter pulse width may be used for the programming signal when programming edge word lines.