Word Line Pulse Width Control for Low-Power Memory Reads
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Solution Overview
Problem
Conventional memory devices consume excessive power due to uniformly long word line pulse widths, which are necessary to ensure accurate read operations across memory cells with varying bit line lengths, leading to inefficient power usage.
Innovation Solution
The memory device generates word line signals with varying pulse widths based on the address of each memory cell, tailoring the pulse width to match the RC characteristics of the corresponding bit line, reducing power consumption without compromising read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If uniformly long word line pulse widths are used to ensure accurate read operations across all memory cells, then read accuracy is maintained, but power consumption increases excessively
Solution Approach 1:
The patent applies local quality by customizing the word line pulse width for each individual memory cell based on its specific bit line length. Instead of using a uniform pulse width for all cells, the system assigns shorter pulse widths to cells with shorter bit lines and longer pulse widths to cells with longer bit lines, optimizing power consumption while maintaining read accuracy for each local condition.
Solution Approach 2:
The patent implements dynamics by making the word line pulse width variable rather than static. The pulse width is dynamically adjusted based on the address of the memory cell being accessed, allowing the system to adapt the pulse duration to the specific RC characteristics of each bit line, thereby reducing unnecessary power expenditure while ensuring reliable reads.
2Reliability
If uniformly long word line pulse widths are used for all memory cells, then read operations are reliable, but power efficiency deteriorates
Solution Approach 1:
The system applies local quality by tailoring the word line pulse width to match the specific RC characteristics of each memory cell's bit line. Cells with shorter bit lines receive shorter pulse widths, while cells with longer bit lines receive longer pulse widths, ensuring each cell operates at optimal power efficiency without compromising read reliability.
Solution Approach 2:
The patent applies parameter changes by varying the pulse width parameter of the word line signal based on the memory cell address. The system changes this temporal parameter dynamically to match the RC time constant of each bit line, optimizing the balance between read reliability and power efficiency for each individual cell.
Data Source
AI summary
A memory device includes a plurality of memory cells, a plurality of word lines, and a word line driver. The word lines are respectively coupled to the memory cells. The word line driver is configured to respectively drive the word lines with word line signals that have varying pulse widths.