Selective Word Line Pulsing to Cut Memory Write Latency
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Solution Overview
Problem
Existing memory devices experience performance degradation due to the need to program dummy data to retired word lines during programming operations, leading to increased write latency and inefficient use of channel resources between the memory sub-system controller and control logic.
Innovation Solution
Selective programming of retired word lines during an erase operation by applying specific voltage pulses to inhibit erasure, allowing the memory device to program a random pattern on these lines and avoid programming dummy data during write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dummy data is programmed on retired word lines during erase operation, then data integrity is maintained, but write latency increases and write performance degrades
Solution Approach 1:
The patent extracts the harmful operation of programming dummy data on retired word lines by identifying and excluding these lines from the erase operation. Retired word lines are selectively omitted from the erase command, allowing the system to skip the time-consuming dummy data programming step while maintaining data integrity through alternative means.
Solution Approach 2:
The patent applies different treatment to different word lines based on their status. Active word lines undergo normal erase operations, while retired word lines are excluded from the erase operation. This local differentiation allows the system to optimize performance for the majority of functional lines while maintaining reliability for data integrity through selective processing.
2Reliability
If dummy data is programmed on retired word lines, then data integrity is maintained, but write performance is degraded
Solution Approach 1:
The patent removes the inefficient dummy data programming step from the erase operation by identifying retired word lines and excluding them from processing. This extraction of the harmful operation directly improves write performance by eliminating the time-consuming dummy data transfer and programming steps.
Solution Approach 2:
The patent discards the unnecessary dummy data programming operation for retired word lines. Instead of programming dummy data, the system discards these lines from the erase operation entirely, recovering write performance by avoiding the time-consuming operation while maintaining data integrity through the exclusion approach.
Data Source
AI summary
Control logic in a memory device causes a first pulse to be applied to a plurality of word lines coupled to respective memory cells in a memory array. The control logic further causes a second pulse to be applied to a first set of word lines of the plurality of word lines. The control logic can cause a third pulse to be applied to a second set of word lines of the plurality of word lines and cause a fourth pulse to be applied to a source line of the memory array to erase the respective memory cells coupled to the first set of word lines and to program the respective memory cells coupled to the second set of word lines.