Word Line Ramping Delay for Low-Current Program Verify
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Solution Overview
Problem
Existing memory devices face challenges in improving efficiency and speed of operation, particularly in non-volatile semiconductor memory, due to inefficiencies in program-verify operations that lead to increased current consumption and uneven programming across memory cells.
Innovation Solution
A memory apparatus and method that includes delaying the ramping of word lines by a predetermined period in specific modes, allowing for precise verification of threshold voltages during program-verify operations, thereby optimizing programming efficiency and reducing current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If word lines are ramped up quickly during program-verify operations, then operation speed is improved, but current consumption increases and programming uniformity deteriorates
Solution Approach 1:
The patent applies dynamic control of the ramping delay period, adjusting it based on the operating mode (normal mode vs. low current consumption mode). In normal mode, a first ramping delay period is used, while in low current consumption mode, a second (different) ramping delay period is applied. This dynamic adjustment allows the system to optimize between speed and current consumption based on operational requirements.
Solution Approach 2:
The patent changes the temporal parameter (ramping delay period) of the word line voltage application. By modifying the delay period between applying verification pulses to selected word lines and ramping unselected word lines, the system controls the timing characteristics to reduce current consumption while maintaining programming uniformity across memory cells.
2Productivity
If verification pulses are applied to selected word lines while ramping unselected word lines, then programming efficiency is improved, but current consumption increases
Solution Approach 1:
The system dynamically adjusts the ramping delay period based on the operating mode. In low current consumption mode, the modified ramping delay allows verification pulses to be applied to selected word lines while controlling the ramping of unselected word lines, thereby maintaining programming efficiency while reducing overall current consumption during the program-verify operation.
3Use of energy by moving object
If ramping delay is increased to reduce current consumption, then energy efficiency is improved, but operation speed decreases
Solution Approach 1:
The patent implements dynamic mode switching with different ramping delay periods. In normal mode, a first ramping delay period is used that prioritizes operation speed. In low current consumption mode, a second ramping delay period is applied that prioritizes energy efficiency. This allows the system to adapt to different operational requirements without compromising either speed or energy efficiency in their respective contexts.
Data Source
AI summary
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means ramps up and applies a read voltage to unselected ones of the word lines while applying verification pulses of program verify voltages each associated with one of the plurality of data states to selected ones of the word lines to determine whether the memory cells connected thereto have the threshold voltage above each of the verify voltages associated with the plurality of data states targeted during a program-verify operation. The control means delays ramping of at least one of the selected ones of the word lines and the unselected ones of the word lines by a predetermined period of time in response to the memory apparatus operating in a predetermined mode.