Word Line Signal Path Layout for Lower DRAM RC Delay
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Solution Overview
Problem
The challenge is to enhance the integration and performance of semiconductor devices, particularly in dynamic random-access memory (DRAM) where reducing element size leads to performance deterioration.
Innovation Solution
A semiconductor device design that includes a first structure with memory cells and a word line crossing the memory block region, and a second structure with a peripheral circuit region vertically overlapping the memory block region. The structures are connected by a word line signal path with routing contacts and interconnection lines, allowing for efficient voltage application to the word line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If element size is reduced to increase integration, then degree of integration is improved, but performance deteriorates due to resistive-capacitive delay and charge sharing
Solution Approach 1:
The word line signal path is segmented into multiple independent paths, each with its own routing contacts. This segmentation allows voltage to be applied to different segments of the word line simultaneously, reducing the overall resistive-capacitive delay and charge sharing time while maintaining high integration density.
Solution Approach 2:
The patent transitions from a single-plane routing approach to a three-dimensional architecture where routing contacts are distributed across multiple vertical layers. This dimensional change enables shorter signal paths and reduced parasitic effects, improving performance without sacrificing integration density.
2Area of moving object
If word line is made thinner to reduce size, then area is reduced, but reliability deteriorates due to thinning or cutting off defects
Solution Approach 1:
The patent implements localized thickening of the word line at critical connection points where routing contacts are formed. This local quality enhancement ensures reliable electrical connection and prevents defects at these vulnerable locations, while the word line maintains its thin profile in the memory cell regions to preserve high integration density.
Solution Approach 2:
The design anticipates potential thinning or cutting off defects by providing redundant routing contact paths and localized reinforcement at critical points. This beforehand cushioning ensures that even if one path is compromised, the word line remains functional, thereby preventing reliability deterioration.
3Speed
If routing contacts are increased to reduce delay, then resistive-capacitive delay is reduced, but device complexity increases
Solution Approach 1:
The routing contacts are designed to serve multiple functions: they provide electrical connection between the bit line and word line, act as vias for vertical signal transmission, and enable independent voltage application to different word line segments. This multi-functionality reduces the need for separate components, thereby limiting the increase in device complexity while achieving reduced resistive-capacitive delay.
Data Source
AI summary
Provided is a semiconductor device. The semiconductor device includes: a first connection region, a first memory block region, and a second connection region sequentially arranged; a first peripheral circuit region vertically overlapping with the first memory block region; first memory cells in the first memory block region; a first word line extending into the first and second connection regions by crossing the first memory block region, and electrically connected to the first memory cells; a first sub-word line driver in the first peripheral circuit region; and a first word line signal path electrically connecting the first word line and the first sub-word line driver. The first word line signal path includes at least one first routing contact coupled to the first word line in the first connection region, and at least one second routing contact coupled to the first word line in the second connection region.