Word Line Activation Tracking for DRAM Row Hammer Mitigation
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Solution Overview
Problem
As memory integration increases, the coupling effect between word lines in memory devices intensifies, leading to the 'row hammering' phenomenon, where data in adjacent memory cells is damaged due to frequent activation, resulting in premature data loss before memory cell refresh.
Innovation Solution
A memory device design that includes edge memory blocks and a control logic circuit to track and manage the activation count of word lines, performing targeted refresh operations to mitigate the row hammering effect by activating specific word lines based on their activation history.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory integration is increased to improve storage capacity, then storage density is improved, but coupling effect between word lines increases causing row hammering phenomenon
Solution Approach 1:
The memory device is divided into multiple memory blocks, with dedicated edge memory blocks positioned at opposite edges of the memory bank array. These edge memory blocks are specifically assigned to store activation count data for different sets of word lines, segmenting the monitoring function across spatially separated units to prevent interference while maintaining comprehensive tracking capability.
Solution Approach 2:
Edge memory blocks serve as intermediary structures between the main memory blocks and the control logic circuit. They store activation count information that mediates the interaction between frequent word line activations and data integrity, allowing the control logic to make informed decisions about refresh operations without direct coupling between adjacent memory cells.
2Reliability
If word line activation is tracked to prevent row hammering, then data integrity is improved, but device complexity increases
Solution Approach 1:
The edge memory blocks perform multiple functions: they store activation count data for word lines, serve as monitoring units for the control logic circuit, and enable refresh operations. This multi-functionality reduces the need for separate dedicated components for each function, thereby managing complexity while maintaining reliability.
Solution Approach 2:
The memory device performs self-monitoring of word line activation counts through the edge memory blocks and control logic circuit. The system automatically tracks activations and triggers refresh operations without external intervention, enabling self-service reliability management that reduces the need for additional complex external control mechanisms.
3Duration of action of stationary object
If targeted refresh operations are performed to mitigate row hammering, then memory cell lifespan is extended, but additional control operations are required
Solution Approach 1:
The control logic circuit continuously monitors activation counts stored in the edge memory blocks and uses this feedback to dynamically determine when refresh operations are needed. This feedback mechanism enables automated, data-driven refresh decisions that extend memory cell lifespan without requiring complex external control, as the system self-regulates based on real-time activation information.
Data Source
AI summary
A memory device including a memory bank array which includes a first edge memory block, a second edge memory block, and a plurality of memory blocks placed between the first edge memory block and the second edge memory block; a plurality of sense amplifiers between the plurality of memory blocks, and that connect a first bit line of a memory block on one side of each of the plurality of sense amplifiers and a first complementary bit line of a memory block on an other side of each of the plurality of sense amplifiers; a first edge sense amplifier connected to a second bit line and a second complementary bit line of the first edge memory block; and a second edge sense amplifier connected to a third bit line and a third complementary bit line of the second edge memory block.


