Self-Aligned Word Line Patterning for Balanced Memory Routing
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Solution Overview
Problem
As the complexity and number of circuit elements in semiconductor memory devices increase, efficient signal routing becomes more difficult, requiring innovative methods to form precise and balanced word line metal layers.
Innovation Solution
The method involves forming oxide and nitride spacers around polysilicon pillars using atomic layer deposition to control layer thickness precisely, enabling an enhanced self-aligned process for patterning word line metal layers and forming separate word lines with balanced widths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithography and etching methods are used to form word lines, then the manufacturing process is simpler, but the precision and balance of word line widths deteriorate as circuit complexity increases
Solution Approach 1:
The word line formation process is segmented into multiple sequential deposition steps (first oxide spacer, nitride spacer, second oxide spacer) rather than relying on a single lithography step. Each spacer layer is deposited independently with precise thickness control, dividing the complex patterning task into manageable segments that can be precisely controlled.
Solution Approach 2:
Sacrificial pillars are formed in advance before the word line metal deposition. These pillars serve as pre-positioned structures that define the future word line locations and widths. The spacers are then deposited around these pre-formed pillars, ensuring precise positioning before the actual word line formation occurs.
2Manufacturing precision
If multiple lithography steps are used to achieve precise word line patterning, then manufacturing precision improves, but the number of process steps and manufacturing complexity increases
Solution Approach 1:
The spacer structures serve dual purposes: they act as both the patterning definition elements and as the actual word line structures. The spacers self-align to the sacrificial pillars through conformal deposition, eliminating the need for separate alignment steps. The process uses the available space around pillars to automatically define precise word line locations and widths.
Solution Approach 2:
The invention changes the fundamental parameter from lithographic resolution (which has physical limits) to thin film deposition thickness control. By using atomic layer deposition or similar precise deposition techniques, word line widths are controlled by film thickness parameters rather than optical resolution parameters, achieving superior precision.
3Reliability
If thicker word line metal layers are used to improve signal routing, then electrical performance improves, but the precision of width control deteriorates
Solution Approach 1:
The process allows for dynamic adjustment of word line thickness by controlling the deposition parameters of each spacer layer. The first and second oxide spacers can be deposited with different thicknesses, and the nitride spacer provides an additional degree of freedom. This dynamic control enables optimization of both electrical performance (through adequate thickness) and precision (through controlled deposition).
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for precise patterning of word line metal layers, improving signal routing efficiency and addressing the challenges of increased complexity in semiconductor memory devices.
Implementation Method 1
forming oxide and nitride spacers around polysilicon pillars using atomic layer deposition to precisely pattern word line metal layers
Data Source
AI summary
A semiconductor memory device manufacturing method includes: sequentially forming a lower oxide layer, a word line metal layer and an upper oxide layer over at least a portion of a memory cell; forming a through hole passing through the upper oxide layer, the word line metal layer and the lower oxide layer to expose the portion of the memory cell; forming a sacrificial pillar into the through hole; removing the upper oxide layer to expose a top portion of the sacrificial pillar; sequentially forming a first oxide spacer sidewall, a nitride spacer sidewall and a second oxide spacer sidewall on a sidewall of the top portion of the sacrificial pillar; removing the nitride spacer sidewall to form a void gap; etching the word line metal layer through the void gap to form separate word lines.