Semiconductor Word Line Separation Layer for Short Circuit Prevention

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Solution Overview

Problem

In the manufacturing of semiconductor devices with stepped structures, there is a risk of short circuits between conductive word lines due to the deposition of thin films on selective regions, which existing technologies fail to adequately prevent.

Innovation Solution

A substrate processing method involving the stacking of insulating and sacrificial layers, generation of a stair structure, and the use of separation layers between conductive word lines, along with selective densification and etching techniques to prevent shorts, including the deposition of a silicon oxide layer on the side walls and replacement with metal to act as word lines.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If thin films are deposited on stepped structures using conventional methods, then film coverage is achieved, but short circuits between conductive word lines occur

Engineering Contradiction:
Improveelectrical insulation between word linesVSAvoidthin film deposition process
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

A separation layer is introduced as an intermediary insulating layer between adjacent conductive word lines on the same level. This separation layer prevents electrical shorts while allowing the thin film deposition process to proceed, thus resolving the contradiction between reliability and ease of manufacture.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The insulating layer is selectively formed only in regions where word lines are in close proximity and short circuit risk exists. This localized approach provides electrical insulation precisely where needed without requiring complete re-engineering of the deposition process.

Inventive Principle:
Principle #3Local quality

2Reliability

If separation layers are added to prevent shorts, then electrical reliability improves, but device structure becomes more complex

Engineering Contradiction:
Improveprevention of short circuitsVSAvoidmulti-layer structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The separation layer is integrated with the existing insulating layer formation process. By combining the separation layer function with the standard insulating layer deposition, the patent adds reliability without proportionally increasing device complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The separation layer is formed in advance during the insulating layer deposition process, before subsequent manufacturing steps. This preliminary action prevents shorts from the outset rather than requiring additional corrective steps later.

Inventive Principle:
Principle #10Preliminary action

3Manufacturing precision

If conventional deposition is used on stepped structures, then manufacturing process remains simple, but selective region deposition control is insufficient

Engineering Contradiction:
Improveselective region film depositionVSAvoiddeposition process control
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The insulating layer is deposited with varying thickness across different regions of the stepped structure. Thinner regions are formed where word lines require separation, while thicker regions provide adequate insulation elsewhere. This local quality variation achieves precise selective region deposition.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

Deposition parameters such as deposition rate, plasma power, and cycle timing are adjusted to control the thickness and distribution of the insulating layer across different regions of the stepped structure, enabling precise selective region deposition.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method effectively prevents electrical shorts between conductive word lines by using separation layers and controlled etching and deposition techniques, ensuring reliable and stable semiconductor device performance.

Implementation Method 1

depositing an insulating layer (e.g., a silicon oxide (SiO) layer and/or a silicon nitride (SiN) layer) on the substrate based on plasma-enhanced atomic layer deposition (PEALD)

Methodology Applied
Scientific EffectPlasma-enhanced atomic layer deposition: Plasma Enhanced Chemical Vapour Deposition

Implementation Method 2

generating a stair structure by etching the stack structures

Methodology Applied
Scientific EffectEtching:

Data Source

PatentUS10504901B2Substrate processing method and device manufactured using the same
Publication Date: 2019.12.10 ASM IP HLDG BV
  • US10504901B2 patent drawing
  • US10504901B2 patent drawing
  • US10504901B2 patent drawing

AI summary

A substrate processing method includes stacking a plurality of stack structures each including an insulating layer and a sacrificial layer, on one another. The method also includes generating a stair structure by etching the stack structures and generating a separation layer on a side surface of the stair structure. The method further includes removing the sacrificial layer and generating conductive word line structures in spaces from which the sacrificial layer is removed. The separation layer is provided between the conductive word line structures.