Detecting Word Line Short Circuits in 3D NAND Memory
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Solution Overview
Problem
Memory devices, particularly those with 3D stacked NAND structures, face challenges in detecting and recovering from short circuits between word lines and source lines, which can lead to incorrect data programming and uncorrectable read errors due to current leakage and voltage interference.
Innovation Solution
A method is introduced to detect short circuits by monitoring program loops and verifying threshold voltages of dummy memory cells, identifying the short-circuited word line, and employing techniques like gate-induced drain leakage (GIDL) or channel gradient erasure to restore proper voltage thresholds, ensuring accurate data storage and retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory devices use 3D stacked NAND structures to increase storage capacity, then storage density is improved, but the risk of short circuits between word lines and source lines increases due to higher complexity and closer spacing
Solution Approach 1:
The patent segments the detection process into multiple phases: initial detection during programming operations, verification through read operations, and identification of specific faulty word lines. This segmentation allows the system to maintain high storage density while systematically managing and detecting short circuit risks in the complex 3D stacked structure.
Solution Approach 2:
The patent performs preliminary detection of short circuits during programming operations before they can cause data corruption. By monitoring program loops and detecting abnormal voltage conditions early, the system prevents reliability issues from developing, allowing the 3D stacked structure to maintain both high capacity and reliability.
2Measurement precision
If the system performs comprehensive detection and verification operations to identify short circuits, then detection accuracy is improved, but operation time and complexity increase
Solution Approach 1:
The patent applies partial detection actions by monitoring only specific parameters (program loop counts, threshold voltages of dummy memory cells) during programming operations, rather than performing exhaustive testing. This approach achieves sufficient detection accuracy without excessive time loss, balancing reliability with operational efficiency.
Solution Approach 2:
The patent implements feedback mechanisms where detection results from program operations inform subsequent read operations and recovery procedures. This feedback loop allows the system to achieve high detection accuracy through iterative verification while minimizing total operation time by avoiding redundant checks.
3Reliability
If the system implements recovery operations to restore voltage thresholds after short circuits, then data integrity is improved, but device complexity and operation time increase
Solution Approach 1:
The patent implements self-service recovery where the memory device automatically detects and recovers from short circuits without external intervention. The system uses built-in dummy memory cells and control circuitry to perform recovery operations, maintaining data integrity while avoiding the need for complex external repair equipment or procedures.
Solution Approach 2:
The patent changes physical parameters (applying specific voltages to word lines, modifying program loop characteristics) to restore proper voltage thresholds after short circuits. By manipulating electrical parameters rather than physical structure, the system maintains data integrity while keeping recovery operations relatively simple and integrated into normal device functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively detects and recovers from short circuits, preventing data corruption and ensuring reliable programming and read operations in memory devices by accurately identifying and correcting voltage issues, thereby maintaining data integrity.
Implementation Method 1
a control circuit applies a read pass voltage to a word line and detects current leakage to the source line
Implementation Method 2
employing techniques like gate-induced drain leakage (GIDL) or channel gradient erasure to restore proper voltage thresholds
Implementation Method 3
channel gradient erasure to restore proper voltage thresholds
Data Source
AI summary
Techniques are described for detecting a short circuit between a word line and a source line in a memory device, and to a method for recovering from such a short circuit. In one aspect, the short circuit is detected in a program operation when a selected word line completes programming after an unusually low number of program loops. A further check is performed to confirm that there is a short circuit. The short circuited word line is then erased and a recovery read is performed for previously-programmed word lines. In another aspect, a short circuit is detected in a read operation.