Word Line Short Detection in 3D NAND Memory Arrays
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Solution Overview
Problem
Existing non-volatile memory systems face challenges in efficiently determining defective word lines and bit lines, which can lead to data loss and operational failures due to shorts and leakage issues within and between blocks, particularly in 3D NAND memory structures.
Innovation Solution
The method involves performing stress operations with varying voltage levels on word lines, select gate lines, and bit lines to introduce voltage differentials and detect defects, including AC stress modes to identify word line to word line shorts within and between blocks, and stress phases to determine bit line to low voltage signal shorts, thereby identifying and marking defective blocks and lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If stress operations with alternating voltage levels are performed on word lines to detect shorts, then detection capability is improved, but device complexity and operation time increase
Solution Approach 1:
The detection process is segmented into distinct phases: intra-block stress operations for detecting shorts within the same block, and inter-block stress operations for detecting shorts between adjacent blocks. Each phase uses specific voltage patterns targeted at particular word line sets, allowing systematic detection without overwhelming complexity.
Solution Approach 2:
Stress operations are performed as a preliminary step before normal write/erase operations. By applying alternating voltage levels to word lines in advance, potential shorts are activated and detected before they can cause data corruption during actual memory operations.
2Reliability
If AC stress modes are performed on all blocks to detect word line shorts, then reliability is improved, but productivity decreases due to extended test time
Solution Approach 1:
Different stress patterns are applied to different blocks based on their position and configuration. Intra-block stress operations target specific word line sets within each block, while inter-block stress operations target word lines at block boundaries. This localized approach ensures comprehensive coverage while reducing redundant testing.
Solution Approach 2:
The stress operations use periodic alternating voltage levels applied to word lines, cycling between high and low voltage states. This periodic stimulation activates potential shorts that may not be detected by static voltage applications, improving detection reliability.
3Measurement precision
If high voltage levels are applied to adjacent word lines concurrently, then detection of leakage paths is improved, but harmful effects increase due to voltage disturbances
Solution Approach 1:
The stress operations are designed to counteract potential leakage paths by applying voltages that stress the insulation between adjacent word lines. By preemptively applying these stress voltages and detecting resulting leakage, the system prevents undetected shorts from causing harm during normal operations.
Solution Approach 2:
The voltage disturbances and leakage currents that would normally be considered harmful effects are actually utilized as detection signals. By monitoring these leakage currents during stress operations, the system converts potentially harmful phenomena into useful diagnostic information for identifying defective word lines.
Data Source
AI summary
A number of techniques for determining defects in non-volatile memory arrays are presented, which are particularly applicable to 3D NAND memory, such as that of the BiCS type. Word line to word shorts within a memory block are determined by application of an AC stress mode, followed by a defect detection operation. An inter-block stress and detection operation can be used determine word line to word line leaks between different blocks. Select gate leak line leakage, both the word lines and other select lines, is consider, as are shorts from word lines and select lines to local source lines. In addition to word line and select line defects, techniques for determining shorts between bit lines and low voltage circuitry, as in the sense amplifiers, are presented.