Word Line Strapping for Memory Cell Resistance Reduction
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Solution Overview
Problem
In semiconductor integrated circuits, the increasing unit-length resistance of conductive structures, such as gate electrodes in memory arrays, leads to longer signal rising or falling times, causing variations in the speed of turning on or off memory cells, which affects the overall performance and efficiency of memory circuits.
Innovation Solution
Implementing word line strapping structures shared between adjacent ROM cells at the first interconnection layer to reduce equivalent unit-length resistance, thereby improving signal transmission speed and consistency across the memory array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the width of conductive structures is reduced to increase functional density, then the number of interconnected devices per chip area increases, but the unit-length resistance of the conductive structure becomes greater
Solution Approach 1:
The conductive structure is divided into multiple segments (first conductive structure, second conductive structure, third conductive structure) arranged in parallel. Each segment carries a portion of the current, effectively reducing the overall resistance while maintaining the same footprint area. This segmentation allows the circuit to achieve lower resistance without increasing the physical dimensions, thus resolving the contradiction between functional density and unit-length resistance.
Solution Approach 2:
Multiple conductive structures are merged into a single equivalent conductive path by connecting them in parallel between the same nodes. The combined conductive structure achieves lower effective resistance than any individual structure, allowing the circuit to maintain high functional density while compensating for the increased unit-length resistance through the collective effect of multiple parallel paths.
2Quantity of substance
If the unit-length resistance of conductive structures increases, then signal rising or falling time becomes longer, but reducing conductive structure width increases functional density
Solution Approach 1:
The conductive path is segmented into multiple parallel structures, each contributing to the overall current flow. This segmentation reduces the effective resistance, thereby decreasing the RC time constant and reducing signal rising and falling times while maintaining high functional density through compact parallel arrangement.
Solution Approach 2:
Instead of increasing the width of a single conductive structure in one dimension, the solution transitions to utilizing multiple parallel conductive structures in the vertical or lateral dimension, effectively adding another dimension to the conductive path design. This approach reduces resistance without sacrificing the compact footprint required for high functional density.
3Quantity of substance
If the width of gate electrode structures is reduced to increase memory cell density, then more memory cells can be packed per area, but the speed of turning on or off pass devices varies across different locations
Solution Approach 1:
The gate electrode structure is segmented into multiple parallel conductive paths that distribute the control signal to different memory cells. This segmentation ensures that signals to cells at different locations traverse paths with more uniform resistance characteristics, reducing location-dependent variations in switching speed while maintaining high cell density through the compact parallel structure.
Solution Approach 2:
The conductive structure is designed with locally optimized parallel paths tailored to specific regions of the memory array. Each local region has its own parallel conductive structures that compensate for local resistance variations, ensuring uniform signal transmission characteristics across different locations while maintaining high overall density.
Data Source
AI summary
A memory circuit includes a first memory cell and a second memory adjacent to the first memory cell. The first memory cell includes a first word line strapping line segment electrically coupled with a pass device of the first memory cell; and a second word line strapping line segment. The second memory cell includes a first word line strapping line segment; and a second word line strapping line segment electrically coupled with a pass device of the second memory cell. The first word line strapping line segment of the first memory cell and the first word line strapping line segment of the second memory cell are connected with each other at a first interconnection layer. The second word line strapping line segment of the first memory cell and the second word line strapping line segment of the second memory cell are connected with each other at the first interconnection layer.