Memory Word Line Switch Layout for Leak Current Suppression
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Solution Overview
Problem
Existing semiconductor storage devices face challenges in reducing chip area to achieve higher density due to significant occupied space by word line switches in the row decoder, which handle high voltages and increase with improved recording density.
Innovation Solution
A semiconductor storage device structure is designed with a first memory cell transistor, a second memory cell transistor, a voltage supply circuit, and word line selection transistors connected by an insulating film, allowing a first wiring to supply a voltage lower than ground, thereby reducing leak current and switch area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the recording density is improved, then the storage capacity increases, but the occupied area of the row decoder increases due to more word line switches
Solution Approach 1:
The patent introduces a new voltage dimension by applying negative voltage to the device isolation region, transforming the traditional single-polarity voltage system into a dual-polarity system. This enables more effective leak current suppression without requiring additional switch area, thereby resolving the contradiction between storage capacity and row decoder area.
Solution Approach 2:
The patent changes the voltage parameter of the device isolation region from ground potential or positive voltage to negative voltage. This parameter change effectively suppresses leak currents between adjacent diffusion layers, allowing for reduced switch area while maintaining high recording density.
2Area of stationary object
If the switch area is reduced to achieve higher density, then the chip area decreases, but the leak current between adjacent diffusion layers increases
Solution Approach 1:
The patent applies negative voltage to the device isolation region, changing the voltage parameter to create a potential barrier that suppresses leak currents. This allows for reduced switch area and smaller chip area while effectively preventing the increase in leak current that would normally occur with higher density configurations.
Solution Approach 2:
The patent proactively applies negative voltage to the device isolation region before read operations to prevent leak currents from occurring in the first place. This preliminary anti-action counteracts the harmful effect of leak current before it can compromise the integrity of adjacent memory cells, enabling safer reduction of switch area.
3Adaptability or versatility
If more word line switches are added to handle high voltages, then the voltage control capability improves, but the occupied space in the row decoder increases
Solution Approach 1:
The patent introduces the device isolation region as an intermediary element that is controlled by negative voltage. This intermediary structure mediates the voltage control between word line switches and the memory cell array, providing enhanced voltage control capability while avoiding the need for additional switch area in the row decoder.
Data Source
AI summary
A semiconductor storage device according to an embodiment includes a first word line connected to a gate of a first memory cell transistor, a second word line connected to a gate of a second memory cell transistor, a first word line selection transistor capable of supplying a voltage from a voltage supply circuit to the first word line, a second word line selection transistor capable of supplying the voltage from the voltage supply circuit to the second word line, an insulating film provided between the first word line selection transistor and the second word line selection transistor, and a first wiring having at least a part provided on the insulating film and extending in a first direction, in which the voltage supply circuit is capable of supplying a first voltage lower than a ground voltage to the first wiring.