Word Line Voltage Control During NAND Verify for Data Retention
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Nonvolatile memory devices face challenges in maintaining the retention characteristics of programmed data due to the influence of adjacent word lines during verify operations, as existing technologies do not effectively account for the program state of these lines without separate read operations.
Innovation Solution
A nonvolatile memory device with a verify circuit that controls the word line voltage and bit line voltage differently during verify operations, taking into account the program state of adjacent word lines, to improve the retention characteristics without requiring a separate read operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a verify operation is performed on a selected memory cell, then the programmed state can be verified, but the retention characteristics deteriorate due to influence from adjacent word lines
Solution Approach 1:
The patent applies different voltage levels to different word lines based on their program state. Specifically, when a verify operation is performed on a selected word line, adjacent word lines that are in a programmed state receive a different voltage (e.g., 0V or a lower voltage) compared to unprogrammed word lines. This localized voltage differentiation prevents charge disturbance in programmed memory cells while maintaining the verify operation on the selected word line, thus resolving the contradiction between verification accuracy and data retention.
2Productivity
If the word line voltage is increased to improve programming efficiency, then the program operation speed increases, but the charge loss in adjacent memory cells increases
Solution Approach 1:
The patent dynamically changes the voltage parameter applied to word lines based on their program state. During a program operation, when a high voltage is applied to a selected word line for programming, adjacent word lines that are already programmed receive a different voltage level (e.g., 0V or a clamped voltage) to prevent charge loss. This parameter differentiation allows high programming speed on the selected word line while protecting adjacent programmed memory cells from charge loss, effectively resolving the contradiction between programming efficiency and charge retention.
Data Source
AI summary
According to an exemplary embodiment of the inventive concept, there is provided a nonvolatile memory device comprising: a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, a memory cell array, in the memory cell region, comprising a plurality of memory cells, a plurality of word lines and a bit line connected to the memory cells, wherein each memory cell is connected to one of the word lines, a voltage generator, in the peripheral circuit region, supplying a plurality of supply voltages to the memory cell array, a control logic circuit, in the peripheral circuit region, programming a selected one of the memory cells connected to a selected one of the word lines into a first program state by controlling the voltage generator, and a verify circuit, in the peripheral circuit region, controlling a verify operation on the memory cell array by controlling the voltage generator, wherein the verify circuit controls a word line voltage applied to at least one unselected word line not to be programmed among the plurality of word lines in the verify operation and a bit line voltage applied to the bit line connected differently from a voltage level of a voltage applied in a read operation of the nonvolatile memory device.