Word Line Voltage Boosting Circuit for Non-Volatile Memory Arrays
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Solution Overview
Problem
Existing non-volatile memory technologies face issues with weakly erased cells, leading to yield loss, data retention problems, and increased erase time, which are costly to address and reduce memory capacity.
Innovation Solution
A word line voltage boosting circuit that alternately switches word lines connected to capacitors or adjacent word lines to boost erase voltage, either using additional capacitors or leveraging existing word line capacitance, allowing for efficient full erasure without additional die area or prolonged operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant rows or sectors are provided to replace weakly erased cells, then yield loss is reduced, but die area increases and cost increases
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the voltage level on word lines during the erase operation. Instead of using redundant rows, the invention modifies the electrical parameters (voltage magnitude and duration) applied to the same word line to ensure complete erasure of all cells, thereby eliminating the need for additional redundant rows and preserving die area.
Solution Approach 2:
The patent implements periodic action through multiple erase pulses applied to the same word line. The erase operation is performed in repeated cycles with verification steps, allowing the system to achieve complete erasure through iterative voltage application rather than relying on static redundant rows, thus maintaining full die area utilization.
2Reliability
If repeated erase operations with verification are performed on weakly erased cells, then data retention is improved, but erase time increases
Solution Approach 1:
The patent applies preliminary action by performing verification checks after each erase pulse to determine whether complete erasure has been achieved. This allows the system to stop the erase operation as soon as the threshold is met, avoiding unnecessary repeated operations and reducing total erase time while ensuring data retention reliability.
Solution Approach 2:
The patent implements feedback through verification operations that monitor the erase status of cells. Based on the verification results, the erase operation is dynamically adjusted or terminated, creating a closed-loop control system that optimizes erase time while guaranteeing complete erasure and proper data retention.
3Reliability
If weakly erased sectors or rows are mapped out and not used, then reliability is improved, but memory capacity is reduced
Solution Approach 1:
The patent applies parameter changes by adjusting the voltage magnitude and pulse duration on word lines to achieve complete erasure of all cells including previously weakly erased ones. This ensures that all memory rows remain usable, maintaining full memory capacity while improving erase reliability through optimized electrical parameters.
4Reliability
If additional capacitors are used to boost word line voltage, then erase reliability is improved, but device complexity and die area increase
Solution Approach 1:
The patent applies universality by designing the word line structure to serve multiple functions: it acts as both the control line for memory cells and as a voltage storage element through its inherent capacitance to adjacent word lines. This eliminates the need for separate dedicated capacitors, reducing device complexity while maintaining the ability to deliver high voltage for reliable erasure.
Solution Approach 2:
The patent merges the function of voltage storage into the word line structure itself by utilizing the parasitic capacitance between adjacent word lines. This combines the control function and the energy storage function into a single integrated structure, avoiding additional components and reducing overall circuit complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively addresses weakly erased cells by boosting erase voltage, reducing yield loss and data retention issues without increasing costs or reducing memory capacity, and can be implemented with minimal additional circuitry, enhancing memory array performance.
Implementation Method 1
The first word line forms a capacitor with the second word line
Implementation Method 2
The alternate switching of the first switch and the second switch boosts the voltage on the first word line
Data Source
AI summary
A first embodiment of a word line voltage boosting circuit for use with an array of non-volatile memory cells has a capacitor, having two ends, connected to the word line. One end of the capacitor is electrically connected to the word line. The other end of the capacitor is electrically connected to a first voltage source. The word line is also connected through a switch to a second source voltage source. A sequencing circuit activates the switch such that the word line is connected to the second voltage source, and the other end of the capacitor is not connected to the first voltage source. Then the sequencing circuit causes the switch to disconnect the word line from the second voltage source, and connect the second end of the capacitor to the first voltage source. The alternate switching of the connection boosts the voltage on the word line. In a second embodiment, a first word line is electrically connected to a first switch to a first voltage source. An adjacent word line, capacitively coupled to the first word line, is electrically connected to a second switch to a second voltage source. A sequencing circuit activates the first switch and the second switch such that the first word line is connected to the first voltage source, and the second word line is disconnected from the second voltage source. Then the sequencing circuit causes the first switch to disconnect the first word line from the first voltage source, and causes the second word line to be electrically connected to the second voltage source. The alternate switching of the connection boosts the voltage on the first word line, caused by its capacitive coupling to the second word line. A boosted voltage on the word line may be used to improve cycling and yield, where the memory cells of the array are of the floating gate type and erase through the mechanism of Fowler-Nordheim tunneling from the floating gate to a control gate which is connected to the word line.