Unselected Word Line Voltage Control for NAND Flash Leakage Reduction
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Solution Overview
Problem
NAND Flash memory devices face leakage current issues during erase operations due to the initial voltage on unselected word lines being added to the channel boosting potential, which limits the shrinkage of driving transistors and increases power consumption.
Innovation Solution
Discharging unselected word lines from the initial voltage to a discharge voltage before the erase operation and floating them during the erase process, then charging them back to the initial voltage at the end, to reduce the total voltage and minimize leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If unselected word lines are kept at initial voltage during erase operation, then the erase operation can be performed, but leakage current increases and driving transistor size shrinkage is limited
Solution Approach 1:
The patent applies preliminary action by discharging unselected word lines to a discharge voltage before the erase operation begins. This pre-action reduces the initial voltage on unselected word lines, thereby reducing the total voltage during erase and minimizing leakage current. The discharge operation is performed in advance (first time period) before the actual erase operation (second time period), allowing the system to start with lower voltage conditions that reduce power loss while maintaining erase functionality.
2Use of energy by stationary object
If unselected word lines are discharged to reduce leakage current, then power consumption decreases, but additional time is required for discharge and charge operations
Solution Approach 1:
The patent implements periodic action by dividing the word line voltage control into distinct time periods: a first time period for discharging unselected word lines to discharge voltage, a second time period for the actual erase operation with floating unselected word lines, and a third time period for charging unselected word lines back to initial voltage. This periodic approach allows the system to optimize power consumption during the erase operation while managing the total operation time through structured voltage transitions.
Data Source
AI summary
In certain aspects, a memory device includes an array of memory cells including a plurality of rows of memory cells, a plurality of word lines respectively coupled to the plurality of rows of memory cells, and a peripheral circuit coupled to the plurality of word lines and configured to perform an erase operation on a selected row of memory cells of the plurality of rows of memory cells. The selected row of memory cells is coupled to a selected word line. To perform the erase operation, the peripheral circuit is configured to discharge an unselected word line coupled to an unselected row of memory cells of the plurality of rows of memory cells from an initial voltage to a discharge voltage in a first time period, and float the unselected word line in a second time period after the first time period.