Memory Device Word Line Voltage Equalization

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Solution Overview

Problem

Existing memory devices, such as NAND flash memory, face challenges in ensuring uniform negative boosting during erase operations, leading to uneven electric fields and potential data reliability issues due to differences in plug critical dimension (CD) sizes among word lines.

Innovation Solution

The memory device employs a peripheral circuit to provide different word line voltages to distinct word line groups based on their plug CD characteristics during erase operations and applies an equalizing voltage during the erase voltage discharging section to ensure uniform negative boosting across all groups.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If different word line groups are provided with different voltages during erase operation, then erase performance is improved, but voltage uniformity deteriorates

Engineering Contradiction:
Improveerase performanceVSAvoidvoltage uniformity
Core Design Contradiction:
ProductivityVSStability of the object's composition

Solution Approach 1:

The word lines are divided into multiple groups (first word line group and second word line group), and each group is provided with different voltages during the erase operation. This segmentation allows optimized erase performance for different word line groups while managing the complexity of voltage distribution.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

An equalizing voltage is applied to all word line groups during the equalizing section to eliminate voltage differences between groups. This ensures uniform voltage distribution and prevents harmful effects caused by voltage non-uniformity, such as uneven negative boosting.

Inventive Principle:
Principle #12Equipotentiality

2Stability of the object's composition

If equalizing voltage is applied during erase voltage discharging section, then voltage uniformity is improved, but operation complexity increases

Engineering Contradiction:
Improvevoltage uniformityVSAvoidoperation complexity
Core Design Contradiction:
Stability of the object's compositionVSDevice complexity

Solution Approach 1:

The equalizing section is combined with the erase voltage discharging section, allowing the equalizing voltage to be applied during the same time period when erase voltage is being discharged. This merging of operations achieves voltage uniformity without requiring additional separate equalizing steps, thereby reducing overall operation complexity.

Inventive Principle:
Principle #5Merging (Combining)

3Adaptability or versatility

If multiple word line groups have different plug CD sizes, then manufacturing flexibility is improved, but negative boosting uniformity deteriorates

Engineering Contradiction:
Improvemanufacturing flexibilityVSAvoidnegative boosting uniformity
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

Different voltage levels are applied to different word line groups based on their specific plug CD characteristics. This local quality approach allows each group to receive optimized voltage treatment, improving erase performance for each group while the equalizing voltage ensures overall uniformity.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The voltage parameter is dynamically adjusted during the erase operation - different voltages are applied to different word line groups during the erasing section, and then an equalizing voltage is applied during the equalizing section. This parameter change strategy ensures both manufacturing flexibility and negative boosting uniformity.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11887694B2Memory device and operating method of the memory device
Publication Date: 2024.01.30 SK HYNIX INC
  • US11887694B2 patent drawing
  • US11887694B2 patent drawing
  • US11887694B2 patent drawing

AI summary

A memory device includes a memory block and a peripheral circuit. The memory block includes a first word line group of word lines included in the memory block and a second word line group of the word lines included in the memory block. The word lines of the first word line group are different from the word lines of the second word line group. The peripheral circuit provides the first word line group and the second word line group with an equalizing voltage during an equalizing section overlapping an erase voltage discharging section for the memory block to constantly keep voltages of the first word line group and the second word line group to the equalizing voltage.