Adjusting Source-Side Word Line Voltage to Reduce Neighbor Interference
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Solution Overview
Problem
Program disturb in memory devices, particularly neighbor word line interference (NWI), leads to inadvertent programming of memory cells, resulting in read errors and reduced threshold voltage margin due to parasitic charges from adjacent word lines during programming and read operations.
Innovation Solution
Adjusting the voltages applied to adjacent word lines during program and read operations by making them symmetric or asymmetric based on the data state, with specific voltage settings for verify and read pass voltages to minimize NWI, particularly when program disturb is likely due to temperature, position in the stack, or number of program-erase cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard voltage levels are applied to unselected word lines during programming operations, then the programming process is simple and fast, but neighbor word line interference occurs causing program disturb and read errors
Solution Approach 1:
The patent applies different voltage levels to different unselected word lines based on their position relative to the selected word line. Specifically, source-side unselected word lines receive a first voltage level while drain-side unselected word lines receive a second voltage level, creating localized voltage control to minimize interference at critical interfaces.
Solution Approach 2:
The patent changes the voltage parameter dynamically during programming operations by selecting from multiple predetermined voltage levels (first voltage level and second voltage level) based on the operational mode (program, verify, read) and the position of unselected word lines, thereby optimizing reliability without requiring complex real-time calculation.
2Manufacturing precision
If symmetric voltages are applied to adjacent word lines during read operations, then the operation is simple, but threshold voltage margin is reduced due to neighbor word line interference
Solution Approach 1:
The patent introduces asymmetric voltage control during read operations by applying different voltage levels to source-side and drain-side unselected word lines. This asymmetry compensates for the threshold voltage shifts caused by neighbor word line interference, thereby maintaining accurate threshold voltage measurement.
Solution Approach 2:
The patent converts the harmful effect of neighbor word line interference into a beneficial compensation mechanism. By measuring the voltage-induced threshold shifts during read operations and using these measurements to adjust subsequent programming operations, the system turns the interference problem into a calibration opportunity that improves overall programming accuracy.
3Productivity
If higher voltages are applied to unselected word lines during programming, then programming speed increases, but program disturb increases due to parasitic charges from adjacent word lines
Solution Approach 1:
The patent applies different voltage levels to different unselected word lines based on their position. Source-side unselected word lines receive a first voltage level that is lower than the maximum programming voltage, while drain-side unselected word lines receive a second voltage level, creating localized voltage control to minimize parasitic charge generation at critical interfaces.
Solution Approach 2:
The patent applies partial voltage (first voltage level and second voltage level) to unselected word lines instead of full programming voltage, which is sufficient for maintaining cell state during programming but insufficient to cause significant parasitic charging, thereby enabling faster programming without excessive program disturb.
Data Source
AI summary
Techniques are described for reducing program disturb including neighbor word interference in a memory device. Voltages applied to the word lines adjacent to the selected word line WLn during program and read operations are adjusted. The adjacent word lines include WLn−1, a source-side adjacent word line of WLn, and WLn+1, a drain side adjacent word line of WLn. In one aspect, VWLn−1<VWLn+1 during the verify tests of the program operation for the data states above the lowest programmed data state and VWLn−1=VWLn+1 during the verify test for the lowest programmed data state. Also, VWLn−1<VWLn+1 during a read operation which distinguishes between the programmed data states and VWLn−1=VWLn+1 during a read operation which distinguishes between erased state and the lowest programmed data state.