Semiconductor Memory Device Word Line Voltage Screening
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Solution Overview
Problem
High-density semiconductor memory devices with vertical-type cell transistors experience increased coupling noise between neighboring word lines, leading to a rapid increase in defective memory cells due to the neighboring gate effect, which affects data retention and read operations.
Innovation Solution
A method involving the application of different driving voltages to selected and neighboring word lines, including boosted and negative voltages, to screen defective memory cells by influencing the threshold voltage of memory cells and detecting leakage currents, thereby identifying and isolating weak cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertical-type cell transistors are used to manufacture high-density semiconductor memory devices, then memory device density is improved, but coupling noise between neighboring word lines increases
Solution Approach 1:
The patent applies different voltage levels to different word lines based on their position and function. Specifically, word lines adjacent to the selected word line receive a different voltage (e.g., lower voltage or negative voltage) compared to the selected word line, creating local voltage differentiation that reduces coupling noise while maintaining high-density vertical transistor architecture
Solution Approach 2:
The patent dynamically changes voltage parameters applied to word lines during operation. By adjusting the voltage level on adjacent word lines relative to the selected word line, the patent modifies the electrical parameters to minimize coupling effects while preserving the high-density structure
2Quantity of substance
If the number of memory cells is increased, then memory capacity is improved, but the number of defective cells increases rapidly
Solution Approach 1:
The patent performs preliminary testing by applying different voltage patterns to word lines before normal operation. This preliminary action identifies potentially defective cells by detecting abnormal leakage currents or threshold voltage shifts that occur when adjacent word lines are subjected to specific voltage conditions
Solution Approach 2:
The patent applies preliminary anti-action by using voltage manipulation to prevent defective cells from being activated. By detecting cells that exhibit abnormal behavior under specific voltage conditions, the system can prevent these cells from being used in normal operation, thereby maintaining high reliability in high-capacity devices
3Reliability
If different driving voltages are applied to selected and neighboring word lines, then defective memory cells are screened, but device complexity increases
Solution Approach 1:
The patent segments the word line control into distinct groups: selected word lines, adjacent word lines, and other word lines, each receiving different voltage levels. This segmentation simplifies the control logic by treating different word line groups differently, rather than requiring individual control of each word line
Solution Approach 2:
The patent uses a universal voltage control scheme where the same voltage patterns are applied systematically across all word line groups. This multi-functional approach allows the same control logic to screen defective cells throughout the entire memory array, reducing overall device complexity through pattern repetition
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively identifies and screens defective memory cells by leveraging the neighboring gate effect, reducing data failure rates and improving memory device reliability through targeted voltage manipulation.
Implementation Method 1
Coupling noise between neighboring word lines may be increased, resulting in defective memory cells. The number of defective cells may be rapidly increased with the increasing level of integration.
Implementation Method 2
A first driving voltage is applied to a first group of word lines. A second driving voltage is applied to a second group of word lines. The first driving voltage has a voltage level different from that of the second driving voltage. Data is read from first memory cells coupled to the first group to determine whether each of the first memory cells is defective.
Data Source
AI summary
A method of testing a semiconductor memory device is provided. Data is written to a plurality of memory cells disposed in a memory cell block of the semiconductor memory device. A first driving voltage is applied to a first group of word lines. A second driving voltage is applied to a second group of word lines. Each word line of the first group of the word lines is interposed between two neighboring word lines of the second group of the word lines. The first driving voltage has a voltage level different from that of the second driving voltage. The data is read from first memory cells coupled to the first group to determine whether each of the first memory cells is defective.