Memory Die Word Line Voltage Transfer for Lower Write Latency
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Solution Overview
Problem
Existing memory systems incur increased latency and NAND bus bandwidth usage due to the need for multiple commands to transfer and set minimum threshold voltages for write operations, which affects performance in high-processing applications like AI, AR, VR, and gaming.
Innovation Solution
The memory system determines and stores minimum threshold voltages directly in a first register of the memory die and transfers them directly to a second register in response to a command, eliminating the need for additional commands and reducing latency and bus traffic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple commands are used to transfer and set minimum threshold voltages, then voltage management accuracy is improved, but write latency increases and NAND bus bandwidth is consumed
Solution Approach 1:
The minimum threshold voltage is determined and stored in a first register of the memory die before the write operation occurs. This preliminary preparation eliminates the need for additional commands during the write process, as the voltage is already ready in the register, thereby reducing write latency while maintaining voltage management accuracy.
Solution Approach 2:
The voltage transfer operation is extracted from the external controller and performed internally within the memory die using on-die registers. This extraction eliminates the need for NAND bus transactions to transfer voltage information, reducing both latency and bandwidth consumption while maintaining the required voltage management precision.
2Measurement precision
If multiple commands are used to transfer and set minimum threshold voltages, then voltage management accuracy is improved, but NAND bus bandwidth usage increases
Solution Approach 1:
The voltage transfer operation is extracted from the external controller and performed internally within the memory die using on-die registers. This extraction eliminates the need for NAND bus transactions to transfer voltage information, reducing both latency and bandwidth consumption while maintaining the required voltage management precision.
Solution Approach 2:
The memory die performs self-service by storing and managing the minimum threshold voltage in its own internal register, eliminating the need for external controller intervention and NAND bus communication for voltage transfer. This self-contained approach maintains voltage management accuracy while completely eliminating the associated bandwidth overhead.
3Ease of operation
If minimum threshold voltage is stored in external controller cache, then ease of operation is improved, but write latency increases
Solution Approach 1:
The voltage storage function is extracted from the external controller cache and relocated to an internal register within the memory die. This extraction brings the voltage information closer to where it is needed (during write operations), eliminating the round-trip time to external memory and significantly reducing write latency while maintaining operational simplicity.
Solution Approach 2:
The voltage storage location is moved from an external dimension (controller cache) to an internal dimension (on-die register). This dimensional change reduces the physical and temporal distance between voltage retrieval and write operation execution, thereby reducing latency while the controller continues to operate simply by issuing the write command.
Data Source
AI summary
Methods, systems, and devices for word line voltage management for a memory system are described. A memory system may determine a minimum threshold voltage for writing to a block of pages of a memory die, store an indication of the minimum threshold voltage in a first register of the memory die, and transfer the indication of the minimum threshold voltage directly from the first register to a second register of the memory die in response to receiving a first command from a controller. The controller may refrain from transmitting a second command prior to a subsequent write command, where the write command may include one or more additional bits indicating that the memory system is to use the minimum threshold voltage to write data to one or more pages of the block.