Self-Aligned Word Line Width Control to Prevent DRAM Shorts
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Solution Overview
Problem
DRAM manufacturers face challenges in minimizing memory cell area due to word line spacing reduction, leading to electrical shorts caused by overlay errors in the lithography process.
Innovation Solution
A method of manufacturing semiconductor devices using a width controlling structure to determine the width of word lines, eliminating the need for photolithography and thereby reducing overlay errors, with the width controlled by the thickness of the width controlling structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If photolithography is used to pattern word lines, then manufacturing process is established, but overlay errors cause electrical shorts between channel and word line
Solution Approach 1:
The patent replaces the photolithography process (optical/mechanical system) with a self-aligned deposition and etch process. The word line pattern is defined by the physical positioning of the first capacitor structure and conformal layer deposition, eliminating overlay errors inherent in photolithography. This substitution resolves the contradiction by maintaining manufacturability while eliminating the source of electrical shorts.
2Area of stationary object
If word line spacing is reduced to minimize memory cell area, then area is reduced, but electrical short between channel and word line increases
Solution Approach 1:
The patent introduces a self-aligned formation process as an intermediary between capacitor structure formation and word line deposition. The conformal layer is deposited uniformly over the first capacitor structure, and the etch process uses this conformal layer as a precise template. This intermediary process ensures that the word line pattern is perfectly aligned with the capacitor structure, preventing electrical shorts even when spacing is reduced for area minimization.
3Length of moving object
If photolithography minimum feature width is reduced for miniaturization, then IC size is reduced, but overlay error impact increases causing electrical short
Solution Approach 1:
The patent implements a self-aligned process where the first capacitor structure itself serves as the alignment reference for forming the word line pattern. The conformal layer deposits uniformly over the capacitor structure, and the subsequent etch process automatically aligns the word line with the capacitor structure without requiring separate photolithography alignment steps. This self-service approach eliminates overlay errors that would otherwise increase as feature dimensions are reduced for miniaturization.
Data Source
AI summary
A method of manufacturing a semiconductor device is provided. The method includes: providing a substrate; forming a metallization layer on the substrate; forming an upper dielectric layer over the metallization layer; forming a first sacrificial layer and a second sacrificial layer, each of which penetrates the upper dielectric layer and the metallization layer; removing the upper dielectric layer; forming a width controlling structure between the first sacrificial layer and the second sacrificial layer, wherein the width controlling structure defines a recess exposing the metallization layer; forming a protective layer within the recess of the width controlling structure; removing the width controlling structure to expose a portion of the metallization layer; and patterning the metallization layer to form a word line between the first sacrificial layer and the second sacrificial layer.