Wordline Bridge in 3D Memory Array Reduces Staircase Footprint
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Solution Overview
Problem
In 3D flash memory arrays, the increasing number of tiers for higher memory density leads to larger wordline access structures, consuming valuable silicon real estate and increasing parasitic capacitances and resistances, which slows down signal transmission and reduces memory cell density.
Innovation Solution
Implementing wordline bridges that allow blocks of memory cells from one tile to share wordline access structures with another tile, reducing the need for redundant access structures and maintaining effective wordline lengths, thereby freeing up silicon space for additional memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If additional tiers of memory cells are added to increase memory density, then memory cell density is improved, but the size of staircase structures increases consuming more silicon real estate
Solution Approach 1:
The patent merges staircase structures from adjacent tiles into shared structures. Specifically, a first staircase structure in a first tile is shared with a second tile through a wordline bridge, and a second staircase structure in the second tile is shared with the first tile. This consolidation reduces the total number of staircase structures needed, freeing up silicon real estate while maintaining access to all wordlines across both tiles.
2Quantity of substance
If additional tiers of memory cells are added to increase memory density, then memory cell density is improved, but parasitic capacitances and resistances increase slowing down signal transmission
Solution Approach 1:
The patent segments the memory array into multiple tiles with localized staircase structures and wordline bridges. By dividing the large memory array into smaller tiles (e.g., 256KB each) connected through wordline bridges, the parasitic capacitances and resistances are distributed and localized rather than accumulated across the entire array. This segmentation maintains signal transmission performance while enabling higher overall memory density.
3Reliability
If traditional wordline access structures are used in each tile, then each tile has independent access capability, but redundant structures consume valuable silicon space
Solution Approach 1:
The patent implements multi-functionality where staircase structures serve multiple tiles simultaneously. A staircase structure in one tile can access wordlines in both its own tile and an adjacent tile through wordline bridges. This universal access capability eliminates the need for duplicate staircase structures in each tile, reducing silicon space consumption by approximately 1-2% while maintaining independent access capability through the bridged connections.
Data Source
AI summary
The present disclosure relates to providing a wordline bridge between wordlines of adjacent tiles of memory cells to reduce the number wordline staircases in 3D memory arrays. An apparatus may include a memory array having memory cells. The memory array includes a first block of pages of the memory cells in a first tile and a second block of pages of the memory cells in a second tile. The apparatus may also include a polysilicon wordline bridge that couples first wordlines of the first block to second wordlines of the second block to couple the first tile to the second tile. The wordline bridge may be formed by applying a hard mask over the first tile, the second tile, and over a portion of polysilicon that connects the first tile to the second tile.