3D NAND Wordline Capacitance Reduction via Air Gaps
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Solution Overview
Problem
Current 3D NAND memory technology faces performance delays due to high wordline capacitance resulting from large conductive sheets separated by multiple dielectric layers, leading to slower read and write speeds.
Innovation Solution
The implementation of memory devices with reduced capacitance is achieved by using pillars with adjacent wordlines separated by dielectric layers containing air gaps or low-k dielectric material, which reduces the overall capacitance of the wordlines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If continuous dielectric layers are used to separate wordlines in 3D NAND arrays, then structural integrity is maintained, but capacitance increases leading to slower read and write speeds
Solution Approach 1:
The patent divides the continuous dielectric layer into discrete, non-contiguous dielectric segments separated by air gaps. This segmentation reduces the overlapping area between adjacent wordlines, thereby reducing parasitic capacitance and improving read/write speeds while maintaining structural integrity through the segmented design.
Solution Approach 2:
The patent introduces air gaps at specific locations between dielectric segments where capacitance reduction is most beneficial. This local modification creates regions of low dielectric constant (air) precisely where needed to reduce capacitive coupling between wordlines, while maintaining continuous dielectric coverage in areas where structural support is required.
2Ease of manufacture
If large conductive sheets are used for wordlines, then manufacturing is simplified, but capacitance increases adding delay to array performance
Solution Approach 1:
The patent segments the continuous dielectric layer into discrete sections with air gaps between them. This approach maintains the simplicity of manufacturing large conductive wordline sheets while reducing the effective capacitive area, thereby decreasing performance delay without significantly complicating the fabrication process.
Solution Approach 2:
The patent changes the dielectric constant parameter by introducing air gaps (εr≈1) between dielectric segments. This parameter modification reduces the overall capacitance of the wordline structure, decreasing the RC time constant and improving array performance speed while maintaining ease of manufacture through standard deposition techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances memory device performance by decreasing the time required for operations, improving read and write speeds, and can be applied to both 3D and 2D memory arrays.
Implementation Method 1
adjacent wordlines of the plurality of wordlines are separated by respective dielectric layers, which include components to reduce capacitance of the plurality of wordlines
Implementation Method 2
The components include air gaps or low-k dielectric material
Data Source
AI summary
Embodiments of the present disclosure are directed towards techniques to provide a memory device with reduced capacitance. In one embodiment, a memory array is formed in a die, and includes one or more pillars and a plurality of wordlines coupled with the one or more pillars. Adjacent wordlines of the plurality of wordlines are separated by respective dielectric layers, which may include components, to reduce capacitance of the plurality of wordlines. The components comprise air gaps or low-k dielectric material. Other embodiments may be described and/or claimed.