Wordline Decoder Gating Circuitry for Selective Refresh Suppression
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Solution Overview
Problem
Existing memory systems face inefficiencies in power consumption due to unnecessary refresh operations in memory devices, particularly after an activate command within a refresh interval.
Innovation Solution
The implementation of gating circuitry in the wordline decoder and refresh control circuitry to selectively suppress refresh operations when unneeded, such as following an activate command within a refresh interval, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If refresh operations are performed for all wordlines during each refresh period, then data integrity is maintained, but power consumption increases due to unnecessary refresh operations after activate commands
Solution Approach 1:
The patent applies local quality by making different parts of the memory system behave differently based on their state. The gating circuitry selectively enables or disables refresh operations for specific wordlines based on whether they have been recently activated. Wordlines that were activated within the refresh period are suppressed from refreshing (saving power), while wordlines that were not activated continue to receive refresh operations (maintaining data integrity). This localized differentiation resolves the contradiction between power savings and data integrity.
Solution Approach 2:
The patent uses preliminary action by setting flag bits in advance to track which wordlines have been activated within a refresh period. Before the refresh operation occurs, the gating circuitry checks these pre-set flags to determine whether to suppress the refresh. This advance preparation allows the system to make informed decisions about which wordlines need refreshing, avoiding unnecessary power consumption while ensuring data integrity for wordlines that require it.
2Use of energy by moving object
If gating circuitry is added to selectively suppress refresh operations, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The patent merges the gating circuitry functionality into the existing wordline decoder structure. Rather than adding completely separate suppression circuitry, the gating logic is integrated with the decode and select logic that already exists in the memory system. The gating circuitry shares resources with the decoder, such as using the same wordline address information and integrating with existing control signals. This merging approach reduces the overall complexity increase compared to adding entirely independent suppression circuitry.
Solution Approach 2:
The gating circuitry is designed to be multi-functional, serving both as part of the wordline selection mechanism and as the refresh suppression mechanism. The same gating logic that enables selective wordline activation during normal operations also performs the refresh suppression function. Additionally, the flag bits used for suppression can serve dual purposes in tracking both activate commands and refresh needs. This universality reduces the need for dedicated separate circuitry, thereby limiting the increase in device complexity.
Data Source
AI summary
A memory device includes an array of storage cells. Each storage cell is coupled to one of multiple bitlines and one of multiple wordlines. A wordline decoder receives wordline address information and selectively activates an addressed wordline corresponding to the received wordline address information. The wordline decoder includes gating circuitry that is operative during a first mode of operation to selectively suppress activation of the addressed wordline during a refresh operation during a current refresh period based on a timing of an activate command associated with the addressed wordline.