Wordline Driver Using NMOS Pull-Down and Resistive Pull-Up
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Solution Overview
Problem
Current memory devices face challenges in achieving higher density without decreasing semiconductor feature sizes, requiring new configurations and approaches for memory component operation to reduce area occupancy while maintaining performance.
Innovation Solution
A wordline driver is implemented using a combination of CMOS transistors and resistors, specifically a pull-down process with NMOS transistors and pull-up resistors, which reduces the area occupied by row and column decoding and wordline driving functions, allowing for efficient selection and deselection of memory cells in phase-change memory or NOR-flash memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If new configurations and approaches are used to increase memory density, then memory area occupancy is reduced, but device complexity increases
Solution Approach 1:
The wordline driver is segmented into separate pull-up and pull-down sections with independent control. The pull-down section uses NMOS transistors while the pull-up section uses PMOS transistors, allowing each section to be optimized independently for area efficiency while maintaining overall driver functionality
Solution Approach 2:
The wordline driver circuit is designed to perform multiple functions within a unified structure: selecting wordlines during read operations, deselecting wordlines during write operations, and providing controlled voltage levels throughout. This multi-functionality reduces the need for separate dedicated circuits for each operation type
2Reliability
If full CMOS transistor configuration is used for wordline driving, then reliability is improved, but area occupancy increases
Solution Approach 1:
Different transistor types are used in different sections of the wordline driver based on local functional requirements. NMOS transistors with lower threshold voltage are used in the pull-down section where fast switching is critical, while PMOS transistors are used in the pull-up section, optimizing each section's performance while reducing overall area
Solution Approach 2:
The circuit utilizes different threshold voltage parameters for NMOS and PMOS transistors to optimize performance. The NMOS transistors have lower threshold voltages enabling faster pull-down operation, while the PMOS transistors provide adequate pull-up strength, allowing the circuit to achieve reliable operation with reduced transistor sizing and area
Data Source
AI summary
Subject matter disclosed herein relates to accessing memory, and more particularly to a wordline driver of same.