Wordline Driver Circuit Transistor Layout Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing wordline driver circuits in memory devices face challenges in efficiently managing and arranging PMOS and NMOS transistors to optimize signal transmission to wordlines, leading to potential electrical property imbalances and increased RC delay.
Innovation Solution
The wordline driver circuit incorporates a combination of PMOS and NMOS transistors, with specific arrangements of PMOS transistors receiving different control signals and NMOS transistors positioned on either side of PMOS transistors, allowing for balanced signal distribution and reduced RC delay by optimizing transistor layout and connection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If PMOS and NMOS transistors are arranged in conventional configurations, then the circuit structure is simple, but electrical property imbalances and increased RC delay occur
Solution Approach 1:
The wordline driver circuit is divided into multiple independent driver units, each containing a PMOS transistor and NMOS transistor pair. This segmentation allows each unit to be optimized independently for electrical balance while maintaining overall circuit functionality, resolving the contradiction between reliability and complexity.
Solution Approach 2:
Different transistor types (PMOS and NMOS) are positioned in specific locations within each driver unit to optimize local electrical properties. The asymmetric placement of transistors relative to the wordline connection point creates locally optimized electrical characteristics that balance rise and fall times, improving overall reliability without requiring complete redesign of the entire circuit.
2Speed
If transistors are positioned to optimize signal transmission, then RC delay is reduced, but transistor layout complexity increases
Solution Approach 1:
Transistors are positioned at different distances from the wordline connection point based on their type and function. PMOS and NMOS transistors are placed asymmetrically to optimize the RC time constant for each switching direction, achieving balanced signal transmission speeds while maintaining a relatively simple overall layout pattern that can be replicated across multiple driver units.
3Reliability
If different control signals are applied to PMOS transistors, then signal distribution balance is improved, but control signal management complexity increases
Solution Approach 1:
The control signal distribution is segmented into separate paths for PMOS and NMOS transistors within each driver unit. This allows independent optimization of control signals for each transistor type, achieving balanced signal distribution while keeping the control logic manageable through modular repetition of the same control pattern across multiple driver units.
Data Source
AI summary
Embodiments provide a wordline driver circuit and a memory. The wordline driver circuit at least includes a first type of wordline drivers and a second type of wordline drivers, wherein each of the wordline drivers includes a PMOS transistor and an NMOS transistor. A first type of PMOS transistors in the first type of wordline drivers and a second type of PMOS transistors in the second type of wordline drivers are configured to receive different first control signals. The first type of PMOS transistors and the second type of PMOS transistors are arranged side by side, a part of the NMOS transistors in the first type of wordline drivers and the second type of wordline drivers are positioned on a side of the first type of PMOS transistors and the second type of PMOS transistors.