Nonvolatile Memory Parity Restore for Adjacent Word Line Failures
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Solution Overview
Problem
As device pitch of wirings in nonvolatile semiconductor memory decreases, maintaining reliability becomes increasingly difficult due to issues such as data loss and failure in writing data to memory cells, particularly due to short circuits between adjacent word lines.
Innovation Solution
A semiconductor memory device is configured with a memory controller that maintains parity data in a memory cache region and uses this parity data to restore data written to first memory cells when failures occur in writing to second memory cells, employing a reproduction information control unit to generate and manage reproduction information for data recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device pitch of wirings is decreased to increase storage capacity, then storage density is improved, but reliability deteriorates due to short circuits between adjacent word lines
Solution Approach 1:
The system performs preliminary actions by maintaining parity data in the memory cache region before actual data writing occurs. When a short circuit between adjacent word lines is detected during writing to second memory cells, the parity data is immediately used to restore the lost data in first memory cells, preventing data integrity failure.
Solution Approach 2:
The system prepares compensatory measures in advance by storing parity data that can compensate for potential data loss. The parity data serves as a cushion against the harmful effect of short circuits, enabling data recovery without requiring additional physical spacing between word lines, thus maintaining high storage density while improving reliability.
2Reliability
If parity data is maintained in memory cache region for data recovery, then reliability is improved, but device complexity increases
Solution Approach 1:
The memory cache region is designed to serve multiple functions: it stores both normal data and parity data required for error recovery. The memory controller's reproduction information control unit performs multiple tasks including generating parity data, detecting writing failures, and restoring lost data. This multi-functionality reduces the need for separate dedicated components, thereby limiting the increase in device complexity while maintaining improved reliability.
Data Source
AI summary
A storage device that can be connected to a host device includes a plurality of nonvolatile memories. Each nonvolatile memory includes first memory cells connected to a first word line and second memory cells connected to a second word line. The second word line is adjacent to the first word line. A controller in the storage device is configured to maintain parity data in a memory area of the host device for the data that has been written to the first memory cells, and, upon detecting a failure in the writing of data to the second memory cells, restore the data written to the first memory cells using the parity data from the memory area of the host device.