Word-Line Pulse Control Circuit for SRAM Write Reliability
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Solution Overview
Problem
Conventional methods for extending word-line pulses in SRAM arrays fail to adequately respond to reductions in power supply voltages, leading to premature activation of sense amplifiers and write operation failures due to linear increases in pulse widths that do not align with voltage reductions.
Innovation Solution
A word-line pulse control circuit incorporating a current tracking circuit and a current mirroring circuit that adjusts the width of word-line pulses by varying the number of current paths activated in response to power supply voltage changes, ensuring the pulses are extended non-linearly to match voltage reductions, thereby optimizing access time and write margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If the widths of word-line pulses are extended linearly in response to power supply voltage reduction, then the access time to SRAM cells is extended, but the increase in pulse widths is insufficient to satisfy the requirement for voltage reduction, causing premature sense amplifier activation and write operation failure
Solution Approach 1:
The patent changes the parameter of pulse width extension from linear to non-linear in response to power supply voltage reduction. The control circuit detects the degree of voltage reduction and accordingly adjusts the pulse width with enhanced extension at lower voltages, ensuring adequate access time while preventing premature sense amplifier activation.
Solution Approach 2:
The patent implements a dynamic control mechanism where the word-line pulse width is adjusted in real-time based on the actual power supply voltage level. The control circuit continuously monitors voltage and dynamically extends the pulse width to compensate for reduced voltage, ensuring write operations remain reliable under varying voltage conditions.
2Productivity
If power supply voltages are reduced to enable circuit scaling, then integration density increases, but read and write margins are reduced, causing errors in read and write operations
Solution Approach 1:
The patent applies preliminary action by extending the word-line pulse width before the write operation completes, ensuring that the sense amplifier is activated at the appropriate time. This pre-adjustment of pulse timing compensates for the reduced voltage margins, allowing reliable write operations even at lower power supply voltages that enable higher integration density.
3Device complexity
If conventional linear pulse width extension is used, then the control circuit is simple, but the pulse width increase cannot keep up with voltage reduction, causing write operation failures
Solution Approach 1:
The patent introduces an intermediary control circuit that sits between the voltage detection mechanism and the word-line pulse generation. This intermediary circuit processes the voltage reduction signal and generates the appropriate non-linear pulse width extension, achieving improved reliability without excessive complexity by using a dedicated control layer.
Data Source
AI summary
An integrated circuit includes a positive power supply node, a current tracking circuit, and a current mirroring circuit including a plurality of current paths coupled in parallel. The currents of the plurality of current paths mirror a current of the current tracking circuit. The current mirroring circuit is configured to turn off the plurality of current paths one-by-one in response to a reduction in a positive power supply voltage on the positive power supply node. The integrated circuit further includes a charging node receiving a summation current of the plurality of current paths, wherein a voltage on the charging node is configured to increase through a charging of the summation current.