Wordline Sidewall Recess for Planar Selector Integration
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Solution Overview
Problem
Non-volatile memory devices face challenges in reducing leakage currents due to process, voltage, and temperature variations, especially in cross-point memory arrays without isolation elements, which affect the reliability and efficiency of memory operations.
Innovation Solution
Integration of Vacancy Modulated Conductive Oxide (VMCO) structures with amorphous silicon and titanium oxide layers, either partially or fully embedded within word line layers, along with the use of selector devices like diodes to reduce leakage currents, and the implementation of vertical bit line architectures to manage memory cell operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If selector devices are integrated within memory hole regions, then leakage current reduction is improved, but fabrication difficulty increases due to dimensional constraints
Solution Approach 1:
The patent transitions from integrating selector devices horizontally within memory hole regions to embedding them vertically within word line layers. This dimensional change allows selector devices to be incorporated without compromising fabrication feasibility, as the vertical embedding approach utilizes the word line layer structure rather than attempting to fit devices into constrained horizontal memory hole spaces.
2Quantity of substance
If process geometries are shrunk to reduce cost per bit, then manufacturing cost is reduced, but variability in memory cell I-V characteristics increases
Solution Approach 1:
The patent introduces selector devices with specific non-linear I-V characteristics into the memory array structure. By embedding these selector devices within word line layers, the system changes the electrical parameters of the memory cells, creating a more favorable I-V characteristic profile that reduces variability even at scaled geometries. The selector devices act as filters that suppress leakage currents and stabilize the overall cell behavior across process, voltage, and temperature variations.
3Area of stationary object
If selector devices are fabricated outside memory hole regions, then area is reduced, but integration complexity increases
Solution Approach 1:
The patent merges the selector device fabrication process with the existing word line layer formation process. By embedding selector devices within the word line layers during standard fabrication steps, the design achieves area reduction without significantly increasing integration complexity. The selector devices share the same fabrication infrastructure and process flows as the word lines, eliminating the need for separate complex integration steps.
Data Source
AI summary
Systems and methods for fabricating a non-volatile memory with integrated selector devices (or steering devices) are described. Each memory cell within a memory array may be placed in series with a selector device, such as a diode or other non-linear current-voltage device, in order to reduce leakage currents through unselected memory cells during a memory operation. In some cases, fabricating a selector device within a memory hole region may be difficult due to the dimensions of the selector device. A wordline sidewall recess process or a wordline sidewall recess with a replacement metal gate process may be used to integrate selector devices with memory cells outside of the memory hole region. By fabricating non-linear selector devices outside of the memory hole region, the area of the memory array may be reduced.