Wordline Segmented SRAM Architecture for RC Delay Reduction
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Solution Overview
Problem
In SRAM design, particularly for FinFET nodes like 7 nm, the high RC delay of wordlines due to increased wire resistance limits performance and area efficiency, making existing solutions like wordline-strapping ineffective for wider memories, and re-buffering introduces additional delay and area inefficiency.
Innovation Solution
The implementation of a wordline segmented architecture, where the wordline is divided into multiple segments with optimized driver strength and routing in higher metal tracks, reducing RC delay while maintaining area efficiency, by grouping memory cells into segments and coupling them to wordlines through edge drivers and re-buffering schemes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If wordline-strapping technique is used to route wordline in higher metal track, then wordline RC delay is reduced, but area efficiency deteriorates and the solution becomes ineffective for wider memories beyond certain CPS range
Solution Approach 1:
The memory array is divided into multiple segments along the wordline direction, with each segment having its own dedicated driver. This segmentation reduces the effective wire length each driver must control, thereby reducing RC delay without requiring complex strapping schemes that would consume additional area.
Solution Approach 2:
The patent introduces segmentation along the wordline direction (adding a dimensional division) to address the RC delay problem. Instead of relying solely on vertical stacking (higher metal tracks), the horizontal segmentation provides an additional degree of freedom to manage signal distribution efficiently.
2Speed
If re-buffering is implemented to reduce wordline RC delay, then performance is improved, but additional delay and area inefficiency are introduced
Solution Approach 1:
Drivers are positioned at the beginning of each memory array segment to proactively drive the wordline signal across the segment. This preliminary action ensures strong signal drive before the signal degrades over the wire length, eliminating the need for re-buffering which would add delay.
Solution Approach 2:
Each memory array segment is self-sufficient with its own driver, eliminating the need for additional re-buffering infrastructure. The segmented architecture allows each segment to service itself without relying on global re-buffering resources that would introduce area overhead and additional delay.
Data Source
AI summary
A memory array including a plurality of memory cells and a plurality of drivers is disclosed. The plurality of memory cells may be arranged in a plurality of rows and a plurality of columns. Memory cells corresponding to a row of the plurality of rows may be logically grouped into a plurality of memory array segments. The plurality of drivers may be coupled to corresponding first ends of corresponding memory array segments of the plurality of memory array segments. Second ends of the corresponding memory array segments may be coupled to second ends of corresponding adjacent memory array segments of the plurality of memory array segments. The second ends of the corresponding memory array segments and the second ends of corresponding adjacent memory array segments may be coupled to corresponding wordlines of a plurality of wordlines.