High-Voltage Shifter Using Timed Support Voltage for Degradation
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Solution Overview
Problem
In 3D NAND flash memory devices, the complexity and size of high-voltage (HV) shifters increase due to transistor degradation, leading to higher chip layout area and cost, as existing solutions require numerous transistors to compensate for degradation, thereby increasing the overall size and complexity of the HV shifter.
Innovation Solution
A high-voltage shifter circuit with a signal transfer circuit and a compensator circuit that includes a P-channel transistor and a high-voltage control signal generator to provide a support voltage for a specified time, reducing the number of transistors and complexity by compensating for transistor degradation, allowing for smaller chip size and reduced complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If numerous transistors are used to compensate for transistor degradation, then reliability is improved, but device complexity and chip layout area increase
Solution Approach 1:
The patent merges the degradation compensation function into the existing HV shifter circuit by reusing the same P-channel transistor that performs signal transfer. The transistor is configured to operate in different modes (linear region for signal transfer, saturation region for compensation) to achieve both functions with a single device, thereby reducing complexity while maintaining reliability.
Solution Approach 2:
The P-channel transistor in the HV shifter is designed to serve multiple functions: it acts as the signal transfer transistor during normal operation and simultaneously serves as the compensation transistor during degradation compensation. This multi-functionality eliminates the need for separate compensation transistors, reducing the overall number of components and circuit complexity.
2Reliability
If numerous transistors are used to compensate for transistor degradation, then reliability is improved, but chip layout area increases
Solution Approach 1:
The patent combines the compensation transistor function with the signal transfer transistor function in a single P-channel device. This merging eliminates the need for additional transistor instances that would occupy extra layout area, thereby maintaining reliability through degradation compensation while minimizing chip area consumption.
Solution Approach 2:
By designing the P-channel transistor to perform both signal transfer and degradation compensation functions, the patent reduces the total transistor count in the HV shifter circuit. This multi-functionality directly translates to reduced chip layout area while preserving the necessary reliability through effective degradation compensation.
3Area of stationary object
If the number of transistors is reduced, then chip layout area decreases, but transistor degradation compensation becomes insufficient
Solution Approach 1:
The patent employs dynamic operation of the P-channel transistor, switching between linear region (for signal transfer) and saturation region (for degradation compensation). This dynamic mode switching enables a single transistor to effectively perform both functions, providing sufficient degradation compensation despite the reduced transistor count and smaller chip area.
Solution Approach 2:
The degradation compensation is implemented periodically through controlled voltage adjustments to the P-channel transistor gate. By applying compensation voltages at appropriate times (during specific operational phases), the system maintains reliability against transistor degradation without requiring continuous additional transistors, thus achieving effective compensation with minimal area overhead.
Data Source
AI summary
Discussed herein are systems and methods for compensating degradation of a transistor in a high-voltage (HV) shifter configured to transfer an input voltage to an access line, such as a global wordline. An embodiment of a memory device comprises a group of memory cells, and a HV shifter circuit including a signal transfer circuit and a compensator circuit. The signal transfer circuit includes a P-channel transistor to transfer a high-voltage input to an access line. The compensator circuit can provide a control signal to the signal transfer circuit by coupling a support voltage higher than a supply voltage (Vcc) to the signal transfer circuit for a specified time period to compensate for degradation of the P-channel transistor. The transferred high voltage is used to charge the access line to selectively read, program, or erase memory cells.