Wordline System Architecture for In-Array I-V Characterization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory circuit technologies cannot perform current-voltage (I-V) characterization on field effect transistors (FETs) in a functional memory array, limiting their operational modes and diagnostic capabilities.
Innovation Solution
A wordline system architecture that includes a twin cell circuit connected to a wordline of a memory array, a source line driver for cell-level current-voltage access, and an integrated analog multiplexer to support multiple operational modes, such as read, program, erase, and current saturation monitoring, enabling I-V characterization of FETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional memory array architecture is used, then the memory array can perform basic read and write operations, but it cannot perform current-voltage characterization on FETs within the array
Solution Approach 1:
The wordline driver circuit is designed to perform multiple functions: standard read/write operations, erase operations with negative voltage, and current-voltage characterization mode. The integrated analog multiplexer allows the same physical circuit to be reconfigured for different measurement modes (Idsatmon, read, program, erase), making the memory array versatile without requiring separate dedicated circuits for each function.
Solution Approach 2:
The system dynamically reconfigures the wordline driver circuit and analog multiplexer based on the desired operational mode. Control signals switch the multiplexer connections and adjust driver circuit parameters to enable different functions (read, program, erase, Idsatmon) on the same hardware, allowing the architecture to adapt its behavior rather than being fixed for a single purpose.
2Measurement precision
If discrete devices are used for I-V characterization, then accurate characterization can be performed, but it cannot be done on FETs in a functional memory array
Solution Approach 1:
The integrated analog multiplexer acts as an intermediary that enables precise measurements within the functional array. It selectively connects different circuit nodes to the measurement path, allowing the characterization equipment to access FETs in their actual operational context within the memory array while maintaining measurement precision through controlled signal routing.
Solution Approach 2:
The measurement and control circuits are nested within the memory array architecture itself. The wordline driver, bitline drivers, and analog multiplexer are integrated components that operate within the array structure, allowing I-V characterization to be performed on FETs while they remain part of the functional memory array rather than requiring extraction to discrete devices.
3Difficulty of detecting and measuring
If the wordline system supports multiple operational modes including erase and I-V characterization, then diagnostic capabilities are improved, but the system complexity increases
Solution Approach 1:
The wordline driver circuit and analog multiplexer are designed as universal components that handle multiple operational modes (read, program, erase, Idsatmon) through software-controlled configuration rather than requiring separate dedicated hardware for each function. This reduces overall system complexity while maintaining comprehensive diagnostic capabilities.
Solution Approach 2:
The system changes operational parameters (voltage levels, multiplexer switch positions, driver circuit configurations) to enable different measurement modes. By dynamically adjusting these parameters based on the desired diagnostic function, the system achieves multiple capabilities without permanently complex hardware architecture.
Data Source
AI summary
The present disclosure relates to integrated circuits, and more particularly, to a wordline system architecture supporting an erase operation and current-voltage (I-V) characterization and methods of manufacture and operation. In particular, the present disclosure relates to a structure including: a twin cell circuit which is connected to a wordline of a memory array; a sourceline driver which is connected to a sourceline of the memory array for providing a cell level current-voltage (I-V) access of the twin cell circuit; and an integrated analog multiplexor which is connected to the twin cell circuit.