Wordlines Over Gate Electrodes for Memory Density
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Solution Overview
Problem
Integrated memory architectures face challenges in scaling to higher densities due to increased wordline resistance and disturbance between neighboring access transistors, as the spacing between active regions narrows, making it difficult to maintain effective wordline width and reduce crosstalk.
Innovation Solution
The solution involves forming wordlines vertically above semiconductor pillars, allowing for thicker widths and lower resistance, and introducing shield lines to reduce disturbance between access transistors, while maintaining efficient packing density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wordlines are formed between neighboring active regions, then the architecture can be scaled to higher densities, but the wordline width becomes narrower and resistance increases
Solution Approach 1:
The patent transitions the wordline configuration from a planar arrangement (between active regions) to a vertical arrangement (above active regions). This dimensional change allows wordlines to maintain adequate width and lower resistance while enabling higher integration density through the vertical stacking of memory structures.
2Object-affected harmful factors
If shield lines are introduced to reduce disturbance between access transistors, then crosstalk is reduced, but valuable real estate is consumed and wordline width is further reduced
Solution Approach 1:
The patent moves shield lines from the lateral plane (between active regions) to the vertical dimension (above active regions), where they can effectively shield against crosstalk without consuming lateral real estate. This allows wordlines to maintain adequate width while still providing crosstalk protection.
Solution Approach 2:
The patent introduces intermediate structures (such as dielectric layers and vertically positioned shield lines) between the wordlines and active regions to mediate and reduce crosstalk disturbance, allowing for tighter packing without directly compromising wordline dimensions.
3Productivity
If active regions are packed tighter to increase density, then integration capacity increases, but disturbance between neighboring access transistors increases
Solution Approach 1:
The patent resolves the crosstalk issue by transitioning shield lines and wordlines to the vertical dimension, allowing lateral packing of active regions to be tightened for higher density while vertical shielding elements prevent crosstalk between neighboring structures.
Data Source
AI summary
Some embodiments include an assembly having bitlines extending along a first direction. Semiconductor pillars are over the bitlines and are arranged in an array. The array includes columns along the first direction and rows along a second direction which crosses the first direction. Each of the semiconductor pillars extends vertically. The semiconductor pillars are over the bitlines. The semiconductor pillars are spaced from one another along the first direction by first gaps, and are spaced from one another along the second direction by second gaps. Wordlines extend along the second direction, and are elevationally above the semiconductor pillars. The wordlines are directly over the first gaps and are not directly over the semiconductor pillars. Gate electrodes are beneath the wordlines and are coupled with the wordlines. Each of the gate electrodes is within one of the second gaps. Shield lines may be within the first gaps.