Work Function Layer Diffusion for Multiple Threshold Voltage Control
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Solution Overview
Problem
Existing processes for forming transistors with multiple threshold voltages are overly complex and costly, with low production efficiency due to the need for multiple mask layers and photolithography processes, leading to potential gaps or voids in the work function layers and metal gate.
Innovation Solution
A method involving the formation of a dielectric layer with six openings, where work function layers are sequentially deposited and diffused using an annealing process to achieve different threshold voltages for PMOS and NMOS transistors, reducing the number of photolithography and etching processes required, and ensuring a dense metal gate fill.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple mask layers and photolithography processes are used to form transistors with different threshold voltages, then different work function layers can be formed for PMOS and NMOS transistors, but the process becomes overly complex and production efficiency decreases
Solution Approach 1:
The patent combines the formation of different work function layers for PMOS and NMOS transistors into a single photolithography and etching process. Instead of using separate mask layers for each transistor type, a unified patterned mask is used to define both PMOS and NMOS regions, allowing simultaneous formation of P-type and N-type work function layers in one process step, thereby simplifying the manufacturing process while maintaining precise threshold voltage control
Solution Approach 2:
The patent applies local quality by forming different work function layers (P-type for PMOS, N-type for NMOS) in specific localized regions defined by the patterned mask. The etching process selectively removes mask material and deposits appropriate work function materials only in the required regions, enabling precise control of threshold voltages for different transistor types without affecting other areas of the device
2Manufacturing precision
If multiple photolithography and etching processes are used to form different work function layers, then different threshold voltages can be achieved, but the number of process steps increases and cost increases
Solution Approach 1:
The patent merges multiple photolithography and etching processes into a single integrated process step. A unified patterned mask defines both PMOS and NMOS transistor regions, and a single etching process selectively deposits P-type work function material in PMOS regions and N-type work function material in NMOS regions simultaneously, reducing the total number of process steps while maintaining precise threshold voltage adjustment capability
Solution Approach 2:
The patent performs preliminary action by pre-defining both PMOS and NMOS transistor regions using a single patterned mask before the work function layer formation. This preliminary patterning establishes the spatial distribution of different transistor types, enabling subsequent selective deposition of appropriate work function materials in one process step rather than requiring multiple sequential patterning operations
3Manufacturing precision
If conventional gate-last process with high-K metal gate is used, then short-channel effect is controlled and gate size is reduced, but the process becomes complicated with low production efficiency
Solution Approach 1:
The patent merges the formation of different work function layers with the high-K metal gate last process into a unified flow. The patterned mask approach enables simultaneous definition of PMOS and NMOS regions, which are then filled with appropriate work function materials and subsequently covered by a common high-K dielectric layer and metal gate electrode, maintaining short-channel effect control while simplifying the overall process and improving production efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Simplifies the process for forming transistors with multiple threshold voltages, improving the performance and stability by reducing the complexity and cost, while preventing gaps or voids in the work function layers and metal gate, resulting in more efficient semiconductor device production.
Implementation Method 1
an annealing process is performed to diffuse a material of the diffusion layer into the first work function layer and the cap layer
Data Source
AI summary
Various embodiments provide semiconductor devices and methods for forming the same. A substrate having a dielectric layer formed thereon is provided. The dielectric layer has six openings. A gate dielectric layer and a cap layer are sequentially formed in each opening of the six openings. A first work function layer is formed in a first opening and a second opening. A diffusion layer is formed in the first opening, a fifth opening, and a sixth opening. A material of the diffusion layer is diffused into the first work function layer and the cap layer, to form a doped work function layer in the first opening and a doped cap layer in the fifth opening and in the sixth opening. A second work function layer is formed in a fourth opening and the fifth opening. A third work function layer and a metal gate are formed in the each opening.