Work Function Metal Gate Stack for Nano-FET Feature Scaling

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

As semiconductor devices continue to shrink in feature size, challenges arise in integrating more components into smaller areas, requiring innovative manufacturing processes to maintain performance and efficiency, particularly in the formation of nano-FETs and FinFETs.

Innovation Solution

The use of advanced manufacturing techniques such as gate-all-around transistor structures, epitaxial source/drain regions, and atomic layer deposition (ALD) processes to form work function metal layers with specific compositions and structures, enabling precise control over channel regions and gate electrodes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but manufacturing precision and process control become more difficult

Engineering Contradiction:
Improveintegration densityVSAvoidfeature size control
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The gate electrode is segmented into multiple layers (first gate electrode layer and second gate electrode layer) with different materials and functions. The first layer provides mechanical support and basic conductivity, while the second layer enables precise work function tuning through atomic layer deposition, allowing independent optimization of each layer's properties to achieve both high integration density and manufacturing precision

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The work function of the gate electrode is precisely controlled by changing the composition parameters of the second gate electrode layer. By adjusting the ratio of titanium to nitrogen in titanium nitride or controlling the thickness and composition of aluminum oxide, the work function can be tuned to specific values, enabling precise electrical characteristics even at reduced feature sizes

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If advanced manufacturing techniques like ALD are used to form work function metal layers, then work function tuning precision is improved, but device complexity and process steps increase

Engineering Contradiction:
Improvework function controlVSAvoidprocess steps
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The second gate electrode layer formed by atomic layer deposition serves multiple functions simultaneously: it provides precise work function control, acts as a barrier layer to prevent diffusion, and maintains electrical conductivity. This multi-functionality reduces the need for separate dedicated layers for each function, thereby managing device complexity while achieving superior work function precision

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The gate electrode uses composite material structure combining titanium nitride and aluminum oxide in the second layer. This composite approach enables precise work function tuning through compositional control while the atomic layer deposition process ensures uniform distribution and intimate mixing of materials, achieving high precision without requiring excessively complex process sequences

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the integration density and performance of semiconductor devices by allowing for precise tuning of work functions and improved strain distribution, leading to better device performance and reliability.

Implementation Method 1

atomic layer deposition (ALD) processes to form work function metal layers with specific compositions and structures

Methodology Applied
Scientific EffectAtomic layer deposition: Chemical Vapour Deposition

Implementation Method 2

epitaxial source/drain regions

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS11908893B2Semiconductor device and method of forming the same
Publication Date: 2024.02.20 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11908893B2 patent drawing
  • US11908893B2 patent drawing
  • US11908893B2 patent drawing

AI summary

A semiconductor device includes source and drain regions, a channel region between the source and drain regions, and a gate structure over the channel region. The gate structure includes a gate dielectric over the channel region, a work function metal layer over the gate dielectric and comprising iodine, and a fill metal over the work function metal layer.